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MS6323ASMGU Datasheet(PDF) 5 Page - MOSA ELECTRONICS |
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MS6323ASMGU Datasheet(HTML) 5 Page - MOSA ELECTRONICS |
5 / 9 page MOSA MS6323 16-Bits Stereo Audio DAC REV1.1 5 www.mosanalog.com TIMING AND DATA FORMAT The MS6323 accepts input serial data formats of 16-bit word length. Left and right data words are time multiplexed. The MSB must always be first. The format of data input is shown in Figs. 2 and 3. With a HIGH level on the word select input (WS), data is placed in the left input register and with LOW level on the WS input, data is placed in the right register (Fig. 1). The data in the input registers are simultaneously latched in the output registers which control the bit switches. Internal bias currents IBL and IBR are each added to the full scale output current IFS in order to achieve the maximum dynamic range at the outputs of OP1 and OP2(Fig. 1). In this way the maximum dynamic range is achieved over the entire power supply range. RIGHT WS BCK DATA LSB MSB t r t HB t f t cr t LB t HW t SW LEFT t SD t HD Fig.2 Timing and input signals. 0 1 2 15 14 13 210 MSB LSB 15 14 13 210 MSB LSB RIGHT LEFT WS BCK DATA Fig.3 Format of input signals. |
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