U2781B

TELEFUNKEN Semiconductors

Rev. A3, 26-Nov-97

6 (10)

Pulse Diagram Phase and Lock Detector

93 7786 e

fp (fvco/Tp)

fr (fosc/Tp)

Vcp

LD

Figure 4.

The LD output is in unlocked condition at low level and the pulsewidth is in reference to the phase respectively fre-

quency difference at the phase detector. If the phase detector output pulses are smaller than 100 ns, the LD output goes

high and indicates “lock” condition.

Test Circuit

Input sensitivity

94 8904

Monitor

Frequency

Counter

RF Test

Generator

Data

Clock

Enable

10 k

U2781B

1n

10 n

1

m

Figure 5.