SDRAM Bus

MCF548x Integrated Microprocessor Electrical Characteristics, Rev. 2.1

Freescale Semiconductor

11

Figure 8. FlexBus Write Timing

9

SDRAM Bus

The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports

either standard SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time.

The SDRAM controller uses SSTL2 and SSTL3 I/O drivers. Both SSTL drive modes are programmable

for either Class I or Class II drive strength.

9.1

SDR SDRAM AC Timing Characteristics

The following timing numbers indicate when data will be latched or driven onto the external bus, relative

to the memory bus clock, when operating in SDR mode on write cycles and relative to SDR_DQS on read

cycles. The MCF548x SDRAM controller is a DDR controller that has an SDR mode. Because it is

designed to support DDR, a DQS pulse must still be supplied to the MCF548x for each data beat of an

SDR read. The MCF548x accomplishes this by asserting a signal called SDR_DQS during read cycles.

Care must be taken during board design to adhere to the following guidelines and specs with regard to the

SDR_DQS signal and its usage.

CLKIN

AD[X:0]

AD[31:Y]

R/W

ALE

TSIZ[1:0]

FBCSn, BE/BWEn

TA

FB1

A[X:0]

A[31:Y]

DATA

FB2

FB3

TSIZ[1:0]

FB3

FB6

FB7

OE