Electronic Components Datasheet Search |
|
FX5959G701ADJT5 Datasheet(PDF) 8 Page - Vishay Siliconix |
|
FX5959G701ADJT5 Datasheet(HTML) 8 Page - Vishay Siliconix |
8 / 11 page www.vishay.com For technical questions, contact FunctionPAK@vishay.com For marketing questions, contact FunctionPAK.marketing@vishay.com Document Number: 10135 82 Revision: 18-Jan-05 FX5959G701 Vishay PIN DESCRIPTION PIN DESCRIPTION SD Logic low on SD pin shuts down the Current Source completely and decreases current consumption to less than 1uA PWM/PSM Logic high =PWM mode, logic low =PSM mode. In PSM mode synchronous rectification is disabled. SYNC Externally controlled synchronization signal. Logic high to low transition forces the clock synchronization. If not used must be connected to Vin or logic high. Vin Input supply voltage GND Ground R1 Included inside the package for fixed voltage. To be added externally for all self-selected voltages. VTP Voltage test point. To test the minimum gap above VL. R0 To be added externally for selected output current. VL Output current. LED connection Vin SD PWM/PSM SYNC GND R1 R0 VTP VL R1 R0 |
Similar Part No. - FX5959G701ADJT5 |
|
Similar Description - FX5959G701ADJT5 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |