6
Leadtrend Technology Corporation
LD7552-DS-00 February, 2005
Application Information
Operation Overview
The LD7552 is optimized to achieve power saving and
minimize the external components counts. The device
incorporated several functions to make it ideal to use in
switching power supplies and switching adaptors.
Under Voltage Lockout (UVLO)
An UVLO comparator is included to detect the voltage on
the Vcc pin to ensure the supply voltage enough to power
on the LD7552 PWM controller and in addition to drive the
power MOSFET.
As shown in Fig. 6, a hysteresis is
provided to prevent the shutdown from the voltage dip
during startup.
The turn-on and turn-off threshold level are
set at 16V and 11.4V, respectively.
Vcc
UVLO(on)
UVLO(off)
t
t
I(Vcc)
startup current
(~uA)
operating current
(~ mA)
Fig. 6
Startup Current and Startup Circuit
The typical startup circuit as shown in Fig. 7 powers ups the
LD7552.
During the startup transient, the Vcc is lower than
the UVLO threshold thus there is no gate pulse generated
from LD7552 to drive power MOSFET.
Therefore, the
current through R1 is to provide the startup current as well
as charge the capacitor C1.
Whenever the Vcc voltage is
higher enough to power on the LD7552 and further to
deliver the gate drive signal, the supply current is provided
from the auxiliary winding of the transformer.
The lower
startup current requirement on the PWM controller will help
to increase the R1 value and then reduce the power
consumption on R1. By using CMOS process and the
special circuit design, the maximum startup current of
LD7552 is only 25 A.
Theoretically, R1 can be very high resistance value.
However, higher R1 will cause longer startup time. By
properly select the value of R1 and C1, it can be optimized
under the consideration of R1 power consumption and the
startup time.
EMI
Filter
R1
OUT
CS
VCC
GND
LD7552
AC
input
C1
Cbulk
D1
Fig. 7
Current Sensing and Leading-edge Blanking
The typical current mode PWM controller feedbacks both
current signal and voltage signal to close the control loop
and achieve regulation. As shown in Fig. 8, the LD7552
detects the primary MOSFET current from the CS pin, which
is not only for the peak current mode control but also for the
pulse-by-pulse
current
limit.
The
maximum
voltage
threshold of the current sensing pin is set as 0.85V. Thus
the MOSFET peak current can be calculated as:
S
)
MAX
(
PEAK
R
V
85
.
0
I
A 250nS leading-edge blanking time is included in the input
of CS pin to prevent the false-trigger caused by the current
spike and further to eliminate the need of R-C filter which is
usually needed in the typical UC384X application (Fig. 9).
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