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UPD4218165LLE-A70 Datasheet(PDF) 1 Page - NEC |
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UPD4218165LLE-A70 Datasheet(HTML) 1 Page - NEC |
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1 / 48 page  © 1995 DATA SHEET The mark shows major revised points. 3.3 V OPERATION 16 M-BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, EDO, BYTE READ/WRITE MODE MOS INTEGRATED CIRCUIT µPD42S18165L, 4218165L Description The µPD42S18165L, 4218165L are 1,048,576 words by 16 bits CMOS dynamic RAMs with optional EDO. EDO is a kind of the page mode and is useful for the read operation. Besides, the µPD42S18165L can execute CAS before RAS self refresh. The µPD42S18165L, 4218165L are packaged in 50-pin plastic TSOP (II) and 42-pin plastic SOJ. Features • EDO (Hyper page mode) • 1,048,576 words by 16 bits organization • Single +3.3 V ±0.3 V power supply • Fast access and cycle time Part number Power consumption Access time R/W cycle time EDO (Hyper page mode) Active (MAX.) (MAX.) (MIN.) cycle time (MIN.) µPD42S18165L-A50, 4218165L-A50 612 mW 50 ns 84 ns 20 ns µPD42S18165L-A60, 4218165L-A60 540 mW 60 ns 104 ns 25 ns µPD42S18165L-A70, 4218165L-A70 504 mW 70 ns 124 ns 30 ns • The µPD42S18165L can execute CAS before RAS self refresh Part number Refresh cycle Refresh Power consumption at standby (MAX.) µPD42S18165L 1,024 cycles /128 ms CAS before RAS self refresh, 0.54 mW CAS before RAS refresh, (CMOS level input) RAS only refresh, Hidden refresh µPD4218165L 1,024 cycles /16 ms CAS before RAS refresh, 1.8 mW RAS only refresh, (CMOS level input) Hidden refresh Document No. M10562EJ8V0DS00 (8th edition) Date Published January 1997 N Printed in Japan The information in this document is subject to change without notice. |
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