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M36L0R8060B1ZAQF Datasheet(PDF) 7 Page - STMicroelectronics |
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M36L0R8060B1ZAQF Datasheet(HTML) 7 Page - STMicroelectronics |
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7 / 18 page  7/18 M36L0R8060T1, M36L0R8060B1 SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram and Table 1., Signal Names, for a brief overview of the signals connect- ed to this device. Address Inputs (A0-A23). Addresses A0-A21 are common inputs for the Flash memory and PSRAM components. The other lines (A23-A22) are inputs for the Flash memory component only. The Address Inputs select the cells in the memory array to access during Bus Read operations. Dur- ing Bus Write operations they control the com- mands sent to the Command Interface of the internal state machine. The Flash memory is ac- cessed through the Chip Enable signal (EF) and through the Write Enable signal (WF), while the PSRAM is accessed through the Chip Enable sig- nal (EP) and the Write Enable signal (WP). Data Input/Output (DQ0-DQ15). The Data I/O output the data stored at the selected address dur- ing a Bus Read operation or input a command or the data to be programmed during a Bus Write op- eration. For the PSRAM component, the upper Byte Data Inputs/Outputs (DQ8-DQ15) carry the data to or from the upper part of the selected address when Upper Byte Enable (UBP) is driven Low. The lower Byte Data Inputs/Outputs (DQ0-DQ7) carry the data to or from the lower part of the selected ad- dress when Lower Byte Enable (LBP) is driven Low. When both UBP and LBP are disabled, the Data Inputs/ Outputs are high impedance. Latch Enable (L). The Latch Enable pin is com- mon to the Flash memory and PSRAM compo- nents. For details of how the Latch Enable signal be- haves, please refer to the datasheets of the re- spective memory components: M69KB096AA for the PSRAM and M30L0R8000T/B0 for the Flash memory. Clock (K). The Clock input pin is common to the Flash memory and PSRAM components. For details of how the Clock signal behaves, please refer to the datasheets of the respective memory components: M69KB096AA for the PSRAM and M30L0R8000T/B0 for the Flash memory. Wait (WAIT). WAIT is an output pin common to the Flash memory and PSRAM components. How- ever the WAIT signal does not behave in the same way for the PSRAM and the Flash memory. For details of how it behaves, please refer to the M69KB096AA datasheet for the PSRAM and to the M30L0R8000T/B0 datasheet for the Flash memory. Flash Chip Enable (EF). The Flash Chip Enable input activates the control logic, input buffers, de- coders and sense amplifiers of the Flash memory component. When Chip Enable is Low, VIL, and Reset is High, VIH, the device is in active mode. When Chip Enable is at VIH the Flash memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. Flash Output Enable (GF). The Output Enable pin controls the data outputs during Flash memory Bus Read operations. Flash Write Enable (WF). The Write Enable controls the Bus Write operation of the Flash memory’s Command Interface. The data and ad- dress inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first. Flash Write Protect (WPF). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is Low, VIL, Lock-Down is enabled and the protection status of the Locked-Down blocks cannot be changed. When Write Protect is at High, VIH, Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (See the Lock Status Table in the M30L0R8000T0/B0 datasheet). Flash Reset (RPF). The Reset input provides a hardware reset of the Flash memory. When Reset is at VIL, the memory is in Reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current IDD2. Refer to Table 6., Flash Memory DC Characteristics - Currents, for the value of IDD2. After Reset all blocks are in the Locked state and the Configura- tion Register is reset. When Reset is at VIH, the device is in normal operation. Exiting Reset mode the device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch En- able is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic with- out any additional circuitry. It can be tied to VRPH (refer to Table 7., Flash Memory DC Characteris- tics - Voltages). PSRAM Chip Enable input (EP). The Chip En- able input activates the PSRAM when driven Low (asserted). When deasserted (VIH), the device is disabled, and goes automatically in low-power Standby mode or Deep Power-down mode. PSRAM Write Enable (WP). Write Enable, WP, controls the Bus Write operation of the PSRAM. When asserted (VIL), the device is in Write mode and Write operations can be performed either to the configuration registers or to the memory array. PSRAM Output Enable (GP). Output Enable, GP, provides a high speed tri-state control, allow- ing fast read/write cycles to be achieved with the common I/O data bus. |
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