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M2051-11I625.0000 Datasheet(PDF) 1 Page - Integrated Circuit Systems |
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M2051-11I625.0000 Datasheet(HTML) 1 Page - Integrated Circuit Systems |
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1 / 12 page  M2050/51/52 Datasheet Rev 1.0 Revised 23Jun2005 Integ r ated Circu it Systems, Inc. ● Communicatio ns Module s ● www.ics t.com ● te l (508) 852-5400 M2050/51/52 SAW PLL FOR 10GBE 64B/66B FEC Integrated Circuit Systems, Inc. Prelimina r y Inf o r m ation GENERAL DESCRIPTION The M2050/51/52 is a VCSO (Voltage Controlled SAW Oscillator) based clock PLL designed for FEC clock ratio translation in 10Gb optical systems such as 10GbE 64b/66b. It supports both mapping and de-mapping of 64b/66b encoding and FEC (Forward Error Correction) clock multiplication ratios. The ratios are pin-selected from pre-programming look-up tables. FEATURES ◆ Integrated SAW delay line; Output of 15 to 700 MHz * ◆ Low phase jitter < 0.5 ps rms typical (12kHz to 20MHz or 50Hz to 80MHz) ◆ Pin-selectable PLL divider ratios support 64b/66b and FEC encoding/decoding ratios: • M2050: Map 10GbE to LAN, 255/238 FEC, or 255/237 FEC • M2051: De-map 10GbE LAN or 255/238 FEC to 10GbE • M2052: De-map 255/237 FEC & 255/238 FEC to 10GbE LAN ◆ Scalable dividers provide further adjustment of loop bandwidth as well as jitter tolerance ◆ LVPECL clock output (CML and LVDS options available) ◆ Reference clock inputs support differential LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL ◆ Loss of Lock (LOL) output pin ◆ Narrow Bandwidth control input (NBW Pin) ◆ Hitless Switching (HS) options with or without Phase Build-out (PBO) available; performance conforms with SONET (GR-253) /SDH (G.813) MTIE and TDEV during reference clock reselection ◆ Single 3.3V power supply ◆ Small 9 x 9 mm SMT (surface mount) package PIN ASSIGNMENT (9 x 9 mm SMT) Figure 1: Pin Assignment * Specify VCSO center frequency at time of order. SIMPLIFIED BLOCK DIAGRAM Figure 2: Simplified Block Diagram Example I/O Clock Frequency Combinations Using M2050 Mapper PLL Base Input Rate (MHz)1 Note 1: Input reference clock can be base rate divided by “Mfin”. Mapper Ratio Mfec / Rfec (Pin Selectable) VCSO* and Base Output Rate (MHz)2 Note 2: Output rate can be base rate divided by “P”. 625.0000 33 / 32 644.5313 625.0000 15 / 14 669.6429 644.5313 15 / 14 690.5692 Table 1: Example I/O Clock Frequency Combinations M 2050 M 2051 M 2052 ( T op View ) 18 17 16 15 14 13 12 11 10 28 29 30 31 32 33 34 35 36 P_SEL0 P_SEL1 nFOUT0 FOUT0 GND nFOUT1 FOUT1 VCC GND FIN_SEL0 FEC_SEL0 FEC_SEL1 LOL NBW VCC DNC DNC DNC NBW M2050, 51, 52 Phase Detector FOUT0 nFOUT0 FEC_SEL1:0 FIN_SEL1:0 Rfec Div MUX 0 REF_SEL DIF_REF0 nDIF_REF0 1 Mfin Divider LUT Mfin Divider (1, 4, 5, 25) P_SEL2:0 DIF_REF1 nDIF_REF1 LOL VCSO Loop Filter TriState FOUT1 nFOUT1 P Divider LUT P Divider (1, 4, 5, 25 or TriState) Mfec and Rfec Divider LUT Mfec Div 3 2 2 M2050/51/52 SAW PLL for 10GbE 64b/66b FEC |
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