M1033-11I155.5200 datasheet(3/14 Pages) ICST

Part #	M1033-11I155.5200

Description	VCSO BASED CLOCK PLL WITH AUTOSWITCH

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Manufacturer	ICST [Integrated Circuit Systems]

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M1033/34 Datasheet Rev 1.0

3 of 14

Revised 07Apr2005

Integr ated Circuit Systems , Inc. ● Netw o r ki ng & C o mmun ica t io ns ● ww w. icst.com ● tel (5 08) 85 2-54 00

M1033/34

VCSO BASED CLOCK PLL WITH AUTOSWITCH

Prod uct Data Sh eet

Integrated

Circuit

Systems, Inc.

DETAILED BLOCK DIAGRAM

Figure 3: Detailed Block Diagram

DIVIDER SELECTION TABLES

M and R Divider Look-Up Tables (LUT)

The MR_SEL3:0 pins select the feedback and reference

divider values M and R to enable adjustment of loop

bandwidth and jitter tolerance. The look-up tables vary

by device variant. M1033 and M1034 are defined in

Tables 3 and 4 respectively.

M1033 M/R Divider LUT

Tables 3 and 4 provide example Fin and phase

detector frequencies with 155.52MHz VCSO

devices (M1033-11-155.5200 and M1034-11-155.5200).

See “Ordering Information” on pg. 14.

M1034 M/R Divider LUT

Phase

Locked

Loop

(PLL)

SAW Delay Line

Phase

Shifter

VCSO

C

POST

C

POST

VC

nVC

R

POST

nOP_OUT

OP_OUT

R

POST

R

LOOP

R

LOOP

C

LOOP

C

LOOP

OP_IN

nOP_IN

PLL

Phase

Detector

Loop Filter

Amplifier

External

Loop Filter

Components

M Divider

R

IN

R

IN

FOUT

nFOUT

P Divider

LUT

P Divider

(1, 2, or TriState)

TriState

P_SEL1:0

NBW

MR_SEL3:0

R Div

MUX

0

REF_SEL

DIF_REF0

nDIF_REF0

1

M / R Divider

LUT

Auto

Ref Sel

1

0

REF_ACK

AUTO

4

Activity

Detector

DIF_REF1

nDIF_REF1

Activity

Detector

LOR

2

0

1

M1033/34

MR_SEL3:0

M Div R Div

Total

PLL

Ratio

Fin for

155.52MHz

VCSO (MHz)

Phase Det.

Freq. for

155.52MHz

VCSO (MHz)

0 0 0 0

8

1

8

19.44

0 0 0 1

32

4

8

19.44

4.86

0 0 1 0

128

16

8

19.44

1.215

0 0 1 1

512

64

8

19.44

0.30375

0 1 0 0

2

1

2

77.76

0 1 0 1

8

4

2

77.76

19.44

0 1 1 0

32

16

2

77.76

4.86

0 1 1 1

128

64

2

77.76

1.215

1 0 0 0

1

155.52

1 0 0 1

4

1

155.52

38.88

1 0 1 0

16

1

155.52

9.72

1 0 1 1

64

1

155.52

2.43

1 1 0 0

Test Mode1

Note 1: Factory test mode; do not use.

N/A

1 1 0 1

1

4

0.25

622.08

155.52

1 1 1 0

4

16

0.25

622.08

38.88

1 1 1 1

16

64

0.25

622.08

9.72

Table 3: M1033 M/R Divider LUT

MR_SEL3:0

M Div R Div

Total

PLL

Ratio

Fin for

155.52MHz

VCSO (MHz)

Phase Det.

Freq. for

155.52MHz

VCSO (MHz)

0 0 0 0

4

1

4

38.88

0 0 0 1

16

4

38.88

9.72

0 0 1 0

64

16

4

38.88

2.43

0 0 1 1

256

64

4

38.88

0.6075

0 1 0 0

2

1

2

77.76

0 1 0 1

8

4

2

77.76

19.44

0 1 1 0

32

16

2

77.76

4.86

0 1 1 1

128

64

2

77.76

1.215

1 0 0 0

1

155.52

1 0 0 1

4

1

155.52

38.88

1 0 1 0

16

1

155.52

9.72

1 0 1 1

64

1

155.52

2.43

1 1 0 0

Test Mode1

Note 1: Factory test mode; do not use.

N/A

1 1 0 1

1

4

0.25

622.08

155.52

1 1 1 0

4

16

0.25

622.08

38.88

1 1 1 1

16

64

0.25

622.08

9.72

Table 4: M1034 M/R Divider LUT

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