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KP023J Datasheet(PDF) 9 Page - Eudyna Devices Inc |
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KP023J Datasheet(HTML) 9 Page - Eudyna Devices Inc |
9 / 13 page Specifications and information are subject to change without notice. 2003-11 Sumitomo Electric Industries, Ltd. 1,Taya-cho, Sakae-ku, Yokohama, 244-8588 Japan Phone: +81-45-853-7263 Fax: +81-45-853-1291 e-mail : GaAsIC-ml@ml.sei.co.jp Web Site: www.sei.co.jp/GaAsIC/ -9- Technical Note P0120003P 800mW GaAs Power FET (Pb-Free Type) SUMITOMO ELECTRIC ♦Caution: Power Supply Sequence P0110003P P0120003P Application Circuit R4 Q1a GND R2 Vgs +6V Vds R1 -5V R3 R5 Q1b GND For safe operation, electric power should be supplied in following sequence. First, the negative voltage should be applied on the gate, and the voltage should be more negative than the pinch-off voltage when you turn on the power supply. Then, drain bias can be applied. Finally, you can turn on the RF signal. When turning off the power supply, the sequence should be (1)RF signal (2)Drain (3)Gate. Gate Voltage 0V Bias Voltage Drain Voltage On On 0V More Than 1mS Off Bias Voltage More Than 1mS Off Gate Voltage 0V Bias Voltage Drain Voltage On On 0V More Than 1mS Off Bias Voltage More Than 1mS Off Gate Voltage 0V Bias Voltage Drain Voltage On On 0V More Than 1mS Off Bias Voltage More Than 1mS Off Vds +5.9V Ids 220mA Q1 UMT1N (Rohm) R1 16Ω 1/10W R2 1.8kΩ 1/10W R3 0.22Ω RL series (SUSUMU) R4 1kΩ 1/10W R5 1.3kΩ 1/10W ♦Bias Circuit [Passive Biasing] If you use a fixed bias circuit, you sometimes need to control the gate bias to get the same Ids, since the devices have some margin of pinch-off voltage (Vp) variation depending on the wafer lots. If you employ a fixed Vgs biasing for your system, you should closely monitor the drain current, particularly when new wafer lots are introduced. If you used Ids other than 220mA, you can calculate the resistance values as follows: R4 set to be 1kΩ [Active Biasing] I1: Ic of Q1a I2:Ic of Q1b We recommend using an active bias circuit, which can eliminate the influence of Vp variation. An example of an active bias circuit called “current mirror ” is shown below. Here, two PNP transistors having the minimum variation of Ibe characteristics are used. These transistors adjust Vgs by changing Vds automatically. It will realize the constant current characteristics, regardless of the temperature. Vbe1: Vbe of Q1aVbe2: Vbe of Q1b R1=(+6V-Vds+Vbe2-Vbe1)/I1=(+6V-Vds)/I1 R2=(Vds-Vbe2)/I1 R3=(+6V-Vds)/(Ids+I2) R5=|-5V-Vgs|/I2 The circuit should be connected directly in line with where the voltage supplies would be normally connected with the application circuit. Of course a matching circuit is required, but it is not shown in this figure. ♦Attention to Heat Radiation In the layout design of the printed circuit board (PCB) on which the power FETs are attached, the heat radiation to minimize the device junction temperature should be taken into account, since it significantly affects the MTTF and RF performance. In any environment, the junction temperature should be lower than the absolute maximum rating during the device operation and it is recommended that the thermal design has enough margin. [Note] In the measurements of RF performance (Pout vs Pin, etc) using the application circuit described before, the active bias circuit herein was not utilized. The application circuits were biased directly from two power supplies. |
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