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 TI
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20 page 
CC2500 Preliminary Data Sheet (rev.1.1.) SWRS040 Page 20 of 77 0 A6 A5 A4 A3 A2 A0 A1 D W 7 D W 6 D W 5 D W 4 D W 3 D W 2 D W 1 D W 0 1 A6 A5 A4 A3 A2 A0 A1 D R 7 D R 6 D R 5 D R 4 D R 3 D R 2 D R 1 D R 0 Read from register: Write to register: Hi-Z X SCLK: CSn: SI SO SI SO Hi-Z t sp t ch t cl t sd t hd t ns X X Hi-Z X S7 S6 S5 S4 S3 S2 S1 S0 Hi-Z S7 S6 S5 S4 S3 S2 S1 S0 S7 S6 S5 S4 S3 S2 S1 S0 S7 X Figure 6: Configuration registers write and read operations (A6 is the “burst” bit) Parameter Description Min Max Units FSCLK SCLK frequency 0 10 MHz tsp,pd CSn low to positive edge on SCLK, in power-down mode TBD - µs tsp CSn low to positive edge on SCLK, in active mode TBD - ns tch Clock high 50 - ns tcl Clock low 50 - ns trise Clock rise time - TBD ns tfall Clock rise time - TBD ns tsd Setup data to positive edge on SCLK TBD - ns thd Hold data after positive edge on SCLK TBD - ns tns Negative edge on SCLK to CSn high. TBD - ns Table 16: SPI interface timing requirements DATA byte 0 ADDR FIFO DATA byte 1 DATAbyte 2 DATA byte n-1 DATAbyte n ... ADDR strobe DATA ADDR strobe ADDRreg ADDRreg n DATAn DATAn+1 DATAn+2 ... ADDR strobe ... CSn: Command strobe(s): Read or write register(s): Read or write consecutive registers (burst): DATA ADDRreg DATA ADDRreg ... DATA byte 0 ADDR FIFO DATA byte 1 Combinations: DATA ADDR reg DATA ADDR reg ADDR strobe ADDR strobe ... Read or write n+1 bytes from/to RF FIFO: Figure 7: Register access types 10.1 Chip Status Byte When the header byte, data byte or command strobe is sent on the SPI interface, the chip status byte is sent by the CC2500 on the SO pin. The status byte contains key status signals, useful for the MCU. The first bit, s7, is the CHIP_RDYn signal; this signal must go low before the first positive edge of SCLK. The CHIP_RDYn signal indicates that the crystal is running and the regulated digital supply voltage is stable. |
