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MN89302 Datasheet(PDF) 5 Page - Panasonic Semiconductor |
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MN89302 Datasheet(HTML) 5 Page - Panasonic Semiconductor |
5 / 11 page For Information Equipment MN89302 Pin Descriptions (continued) Pin No. Symbol I/O Level Function Description 94 LCAS O CMOS Lower Column Address Strobe (LCAS) This output is the strobe signal for the lower column address latch. In the 2WE mode, however, it functions as the LWE signal. 92 WE O CMOS Write Enable This output is the data write signal. In the 2WE mode, however, it functions as the UWE signal. 112 to 97 MD[15:0] I/O TTL Memory Data These pins represent the data bus to the DRAM. 26 BIOSEN O CMOS BIOS Enable This output enables ROM BIOS output. 49 BACKON O CMOS Backlight ON This output requests backlighting. "L" level: OFF; "H" level: ON 50 LCDON O CMOS LCD Drive ON This output requests power-ON for the LCD panel. "L" level: OFF; "H" level: ON 51 LOGICON O CMOS LCD Logic ON This output requests power-ON for LCD panel logic circuits. "L" level: OFF; "H" level: ON 56 LP O CMOS Line Pulse This output provides pulses indicating the end of a line of the LCD panel. 55 FP O CMOS Frame Pulse This output provides pulses indicating the start of a frame of the LCD panel. 54 DISP O CMOS Display Enable This output enables the LCD display. An external RAMDAC uses this signal as a blanking signal. A TFT LCD uses it as an enable signal. 57 DCLK O CMOS Data Shift Clock This pin provides a data shift clock signal for an STN LCD panel or a dot clock signal for a TFT LCD panel or external RAMDAC. 77 to 70 UD[7:0] O CMOS Upper Data[7:0] 67 to 60 LD[7:0] O CMOS Lower Data[7:0] This pins provide display data. Usage varies with the LCD panel type. |
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