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MX29F040CPI-70 Datasheet(PDF) 11 Page - Macronix International |
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MX29F040CPI-70 Datasheet(HTML) 11 Page - Macronix International |
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11 / 38 page  11 P/N:PM1201 REV. 1.0, DEC. 20, 2005 MX29F040C Q5 Exceeded Timing Limits Q5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions Q5 will produce a "1". This time-out condition indicates that the program or erase cycle was not suc- cessfully completed. Data# Polling and Toggle Bit are the only operating functions of the device under this con- dition. If this time-out condition occurs during sector erase op- eration, it specifies that a particular sector is bad and it may not be reused. However, other sectors are still func- tional and may be used for the program or erase opera- tion. The device must be reset to use other sectors. Write the Reset command sequence to the device, and then execute program or erase command sequence. This allows the system to continue to use the other active sectors in the device. If this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or com- bination of sectors are bad. If this time-out condition occurs during the byte program- ming operation, it specifies that the entire sector con- taining that byte is bad and this sector may not be re- used, (other sectors are still functional and can be re- used). The time-out condition may also appear if a user tries to program a non blank location without erasing. In this case the device locks out and never completes the Au- tomatic Algorithm operation. Hence, the system never reads a valid data on Q7 bit and Q6 never stops toggling. Once the Device has exceeded timing limits, the Q5 bit will indicate a "1". Please note that this is not a device failure condition since the device was incorrectly used. DATA PROTECTION The MX29F040C is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transi- tion. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of spe- cific command sequences. The device also incorporates several features to prevent inadvertent write cycles re- sulting from VCC power-up and power-down transition or system noise. Q3 Sector Erase Timer After the completion of the initial sector erase command sequence, the sector erase time-out will begin. Q3 will remain low until the time-out is complete. Data# Polling and Toggle Bit are valid after the initial sector erase com- mand sequence. If Data# Polling or the Toggle Bit indicates the device has been written with a valid erase command, Q3 may be used to determine if the sector erase timer window is still open. If Q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data# Polling or Toggle Bit. If Q3 is low ("0"), the device will accept addi- tional sector erase commands. To insure the command has been accepted, the system software should check the status of Q3 prior to and following each subsequent sector erase command. If Q3 were high on the second status check, the command may not have been accepted. WRITE PULSE "GLITCH" PROTECTION Noise pulses of less than 5ns (typical) on CE# or WE# will not initiate a write cycle. LOGICAL INHIBIT Writing is inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle CE# and WE# must be a logical zero while OE# is a logical one. POWER SUPPLY DECOUPLING In order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected be- tween its VCC and GND. |
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