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MX26LV040PC-70G Datasheet(PDF) 8 Page - Macronix International |
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MX26LV040PC-70G Datasheet(HTML) 8 Page - Macronix International |
8 / 40 page 8 P/N:PM1118 MX26LV040 REV. 1.0, NOV. 08, 2004 mand sequence into the command register. SET-UP AUTOMATIC CHIP/SECTOR ERASE COMMANDS Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command 80H. Two more "unlock" write cycles are then followed by the chip erase command 10H or sector erase command 30H. The Automatic Chip Erase does not require the device to be entirely pre-programmed prior to executing the Auto- matic Chip Erase. Upon executing the Automatic Chip Erase, the device will automatically program and verify the entire memory for an all-zero data pattern. When the device is automatically verified to contain an all-zero pat- tern, a self-timed chip erase and verify begin. The erase and verify operations are completed when the data on Q7 is "1" at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations. When using the Automatic Chip Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). If the Erase operation was unsuccessful, the data on Q5 is "1"(see Table 7), indicating the erase operation ex- ceed internal timing limit. The automatic erase begins on the rising edge of the last WE# or CE# pulse, whichever happens first in the com- mand sequence and terminates when the data on Q7 is "1" and the data on Q6 stops toggling for two consecu- tive read cycles, at which time the device returns to the Read mode. |
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