MX26LV004BQC-55 datasheet(10/43 Pages) MCNIX

Part #	MX26LV004BQC-55

Description	4M-BIT [512K x 8] CMOS SINGLE VOLTAGE 3V ONLY HIGH SPEED eLiteFlashTM MEMORY

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Manufacturer	MCNIX [Macronix International]

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P/N:PM1099

MX26LV004T/B

REV. 1.0, NOV. 08, 2004

READ/RESET COMMAND

The read or reset operation is initiated by writing the

read/reset command sequence into the command reg-

ister. Microprocessor read cycles retrieve array data.

The device remains enabled for reads until the command

register contents are altered.

If program-fail or erase-fail happen, the write of F0H will

reset the device to abort the operation. A valid com-

mand must then be written to place the device in the

desired state.

SILICON-ID READ COMMAND

Flash memories are intended for use in applications where

the local CPU alters memory contents. As such, manu-

facturer and device codes must be accessible while the

device resides in the target system. PROM program-

mers typically access signature codes by raising A9 to

a high voltage (VID). However, multiplexing high volt-

age onto address lines is not generally desired system

design practice.

The MX26LV004T/B contains a Silicon-ID-Read opera-

tion to supple traditional PROM programming methodol-

ogy. The operation is initiated by writing the read silicon

ID command sequence into the command register.

SET-UP AUTOMATIC CHIP/SECTOR ERASE

COMMANDS

Chip erase is a six-bus cycle operation. There are two

"unlock" write cycles. These are followed by writing the

"set-up" command 80H. Two more "unlock" write cycles

are then followed by the chip erase command 10H or

sector erase command 30H.

The Automatic Chip Erase does not require the device

to be entirely pre-programmed prior to executing the Au-

tomatic Chip Erase. Upon executing the Automatic Chip

Erase, the device will automatically program and verify

the entire memory for an all-zero data pattern. When the

device is automatically verified to contain an all-zero

pattern, a self-timed chip erase and verify begin. The

erase and verify operations are completed when the data

on Q7 is "1" at which time the device returns to the

Read mode. The system is not required to provide any

control or timing during these operations.

When using the Automatic Chip Erase algorithm, note

that the erase automatically terminates when adequate

erase margin has been achieved for the memory array

(no erase verification command is required).

If the Erase operation was unsuccessful, the data on

Q5 is "1"(see Table 7), indicating the erase operation

exceed internal timing limit.

The automatic erase begins on the rising edge of the

last WE# or CE# pulse, whichever happens first in the

command sequence and terminates when the data on

Q7 is "1" and the data on Q6 stops toggling for two con-

secutive read cycles, at which time the device returns

to the Read mode.

operation, the RY/BY# pin remains a "0" (busy) until the

internal reset operation is complete, which requires a time

of tREADY (during Embedded Algorithms). The system

can thus monitor RY/BY# to determine whether the reset

operation is complete. If RESET# is asserted when a

program or erase operation is completed within a time of

tREADY (not during Embedded Algorithms).The system

can read data tRH after the RESET# pin returns to VIH.

Refer to the AC Characteristics tables for RESET#

parameters and to Figure 14 for the timing diagram.

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MX26LV004BQC-55 Datasheet(PDF) 10 Page - Macronix International

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Similar Part No. - MX26LV004BQC-55

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