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MX26LV160AT Datasheet(PDF) 6 Page - Macronix International

Part No. MX26LV160AT
Description  16M-BIT [2Mx8/1Mx16] CMOS SINGLE VOLTAGE 3V ONLY BOOT SECTOR HIGH SPEED eLiteFlashTM MEMORY
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Maker  MCNIX [Macronix International]
Homepage  http://www.macronix.com
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 6 page
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P/N:PM1123
MX26LV160AT/AB
REV. 1.1, NOV. 18, 2004
AUTOMATIC PROGRAMMING
The MX26LV160AT/AB is word/byte programmable us-
ing the Automatic Programming algorithm. The Auto-
matic Programming algorithm makes the external sys-
tem do not need to have time out sequence nor to verify
the data programmed.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm requires the
user to only write program set-up commands (including
2 unlock write cycle and A0H) and a program command
(program data and address). The device automatically
times the programming pulse width, provides the pro-
gram verification, and counts the number of sequences.
A status bit similar to DATA# polling and a status bit
toggling between consecutive read cycles, provide feed-
back to the user as to the status of the programming
operation. Refer to write operation status, table 7, for more
information on these status bits.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
The Automatic Erase algorithm automatically programs
the entire array prior to electrical erase. The timing and
verification of electrical erase are controlled internally
within the device.
AUTOMATIC SECTOR ERASE
The MX26LV160AT/AB is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. The Automatic Sector
Erase algorithm automatically programs the specified
sector(s) prior to electrical erase. The timing and verifi-
cation of electrical erase are controlled internally within
the device. An erase operation can erase one sector,
multiple sectors, or the entire device.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stan-
dard microprocessor write timings. The device will auto-
matically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number of
sequences. A status bit toggling between consecutive
read cycles provides feedback to the user as to the sta-
tus of the erasing operation.
Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry. During write cycles, the command register inter-
nally latches address and data needed for the program-
ming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge of WE# or CE#, whichever
happens first.
MXIC's high speed Flash technology combines years of
EPROM experience to produce the highest levels of
quality, reliability, and cost effectiveness. The
MX26LV160AT/AB electrically erases all bits simulta-
neously using Fowler-Nordheim tunneling. The bytes are
programmed by using the EPROM programming mecha-
nism of hot electron injection.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.
AUTOMATIC SELECT
The auto select mode provides manufacturer and de-
vice identification, protection verification, through identi-
fier codes output on Q7~Q0.This mode is mainly adapted
for programming equipment on the device to be pro-
grammed with its programming algorithm.When program-
ming by high voltage method, automatic select mode re-
quires VID (11V to 12V) on address pin A9 and other
address pin A6, A1 and A0 as referring to Table 3. In
addition, to access the automatic select codes in-sys-
tem, the host can issue the automatic select command
through the command register without requiring VID, as
shown in table 4.
To verify whether or not sector being protected, the sec-
tor address must appear on the appropriate highest order
address bit (see Table 1 and Table 2).The rest of address
bits, as shown in Table 3, are don't care. Once all neces-
sary bits have been set as required, the programming
equipment may read the corresponding identifier code on
Q7~Q0.




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