MX26F640J3TC-10 datasheet(6/47 Pages) MCNIX

Part #	MX26F640J3TC-10

Description	64M [x8/x16] SINGLE 3V PAGE MODE eLiteFlashTM MEMORY

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Manufacturer	MCNIX [Macronix International]

Direct Link	http://www.macronix.com

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6 / 47 page

6

P/N:PM1114

REV. 0.00, JUN. 30, 2004

MX26F640J3

R

NOTES:

1. See Table 1 on page 7 for valid CE configurations.

2. OE and WE should never be enabled simultaneously.

3. DQ refers to Q0-Q7 if BYTE is low and Q0-Q15 if BYTE is high.

4. Refer to DC Characteristics. When VPEN < VPENLK , memory contents can be read, but not altered.

5. X can be VIL or VIH for control and address pins, and VPENLK or VPENH for VPEN . See DC Characteristics for

VPENLK and VPENH voltages.

6. In default mode, STS is VOL when the WSM is executing internal block erase, program, or lock-bit configuration

algorithms. It is VOH when the WSM is not busy, or in reset/power-down mode.

7. High Z will be VOH with an external pull-up resistor.

8. See Section , "Read Identifier Codes" for read identifier code data.

9. See Section , "Read Query Mode Command" for read query data.

10.Command writes involving block erase, program, or lock-bit configuration are reliably executed when VPEN=

VPENH and VCC is within specification.

11.Refer to Table 3 on page 10 for valid DIN during a write operation.

Table 2. Bus Operations

Command

Read

Output

Standby RESET Read ID

Read

Write

Sequence

Array

Disable

Mode/

Query

Status

Power

(WSM off) (WSM on)

Down

Mode

Notes

4,5,6

6,10,11

RESET

VIH

VIL

VIH

CE0,CE1,CE2(1) Enabled Enabled Disabled X

Enabled

Enabled Enabled

Enabled

OE (2)

VIL

VIH

X

VIL

VIH

WE (2)

VIH

X

VIH

VIL

Address

X

See

X

Figure 2

Table 6

VPEN

X

VPENH

Q (3)

Data out High Z

High Z

High Z Note 8

Note 9

Data out

Q7=Data out

Data in

Q15-8=High Z

Q6-0=High Z

STS

High Z

X

High Z High Z

High Z

X

(default mode)

(7)

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