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MX25L4005ZMC-15G Datasheet(PDF) 2 Page - Macronix International |
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MX25L4005ZMC-15G Datasheet(HTML) 2 Page - Macronix International |
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2 / 41 page  2 P/N: PM1236 REV. 1.1, SEP. 30, 2005 MX25L4005 PIN CONFIGURATIONS SYMBOL DESCRIPTION CS# Chip Select SI Serial Data Input SO Serial Data Output SCLK Clock Input HOLD# Hold, to pause the device without deselecting the device WP# Write Protection VCC + 3.3V Power Supply GND Ground PIN DESCRIPTION GENERAL DESCRIPTION The MX25L4005 is a CMOS 4,194,304 bit serial Flash memory, which is configured as 524,288 x 8 internally. The MX25L4005 feature a serial peripheral interface and soft- ware protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). SPI access to the device is enabled by CS# input. The MX25L4005 provide sequential read operation on whole chip. After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or byte /sector/block locations will be executed. Program command is executed on page (256 bytes) basis, and erase command is executes on chip or sector(4K-bytes) or block(64K-bytes). To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. When the device is not in operation and CS# is high, it is put in standby mode and draws less than 10uA DC current. The MX25L4005 utilize MXIC's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. 8-PIN SOP (150/200mil) 8-LAND SON (6x5mm) 1 2 3 4 CS# SO WP# GND 8 7 6 5 VCC HOLD# SCLK SI |
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