7

P/N: PM0943

REV. 1.0, SEP. 29, 2004

MX25L6402

ADDRESS SEQUENCE

The address assignment is described as follows :

BA: Byte address Bit sequence:

X

A6

A5

A4

A3

A2

A1

A0

AD1:First Address Bit sequence:

X

X

A22

A21

A20

A19

A18

A17

AD2:Second Address Bit sequence:

A16

A15

A14

A13

A12

A11

A10

A9

AD3:Thrid Address Bit sequence:

X

X

X

X

X

X

A8

A7

DATA SEQUENCE

Output data is serially sent out through SO pin, synchronized with the rising edge of SCLK, whereas input data is serially

read in through SI pin, synchronized with the rising edge of SCLK. The bit sequence for both input and output data is bit

7 (MSB) first, then bit 6, bit 5, ...., and bit 0.(LSB)

RESET OPERATION

The RESET pin provides a hardware method of resetting the device to reading array data. When the RESET pin is driven

low for at least a period of tRP, the device immediately terminates any operation in progress, tri-states all output pins, and

ignores all commands for the duration of the RESET pulse. The device also resets the internal state machine to reading

array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command

sequence, to ensure data integrity. Current is reduced for the duration of the RESET pulse. When RESET is held at VSS

+ 0.3V, the device draws reset current (ICC4). If RESET is held at VIL but not within VSS + 0.3V, the reset current will

be greater. The RESET pin may be tied to system reset circuitry. A system reset would that also reset the SPI memory.

Refer to the AC Characteristics tables for RESET parameters.