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DS26303L-75+ Datasheet(PDF) 4 Page - Maxim Integrated Products |
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DS26303L-75+ Datasheet(HTML) 4 Page - Maxim Integrated Products |
4 / 97 page DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 4 of 97 LIST OF FIGURES Figure 3-1. Block Diagram ........................................................................................................................................... 9 Figure 3-2. Receive Logic Detail................................................................................................................................ 10 Figure 3-3. Transmit Logic Detail............................................................................................................................... 10 Figure 4-1. 160-Pin PBGA Pin Assignment............................................................................................................... 19 Figure 4-2. 144-Pin eLQFP Pin Assignment ............................................................................................................. 20 Figure 4-3. Serial Port Operation for Write Access ................................................................................................... 22 Figure 4-4. Serial Port Operation for Read Access with CLKE = 0 ........................................................................... 22 Figure 4-5. Serial Port Operation for Read Access with CLKE = 1 ........................................................................... 23 Figure 4-6. Interrupt Handling Flow Diagram ............................................................................................................ 24 Figure 6-1. Pre-Scaler PLL and Clock Generator...................................................................................................... 53 Figure 6-2. T1 Transmit Pulse Templates ................................................................................................................. 55 Figure 6-3 E1 Transmit Pulse Templates .................................................................................................................. 56 Figure 6-4. LIU Front End .......................................................................................................................................... 57 Figure 6-5. HPS Logic ............................................................................................................................................... 62 Figure 6-6. HPS Block Diagram................................................................................................................................. 62 Figure 6-7. Jitter Attenuation ..................................................................................................................................... 63 Figure 6-8. Analog Loopback..................................................................................................................................... 64 Figure 6-9. Digital Loopback...................................................................................................................................... 65 Figure 6-10. Remote Loopback ................................................................................................................................. 65 Figure 6-11. PRBS Synchronization State Diagram.................................................................................................. 67 Figure 6-12. Repetitive Pattern Synchronization State Diagram............................................................................... 68 Figure 7-1. JTAG Functional Block Diagram ............................................................................................................. 70 Figure 7-2. TAP Controller State Diagram................................................................................................................. 73 Figure 10-1. Intel Nonmuxed Read Cycle ................................................................................................................. 80 Figure 10-2. Intel Mux Read Cycle ............................................................................................................................ 81 Figure 10-3. Intel Nonmux Write Cycle...................................................................................................................... 83 Figure 10-4. Intel Mux Write Cycle ............................................................................................................................ 84 Figure 10-5. Motorola Nonmux Read Cycle .............................................................................................................. 86 Figure 10-6. Motorola Mux Read Cycle ..................................................................................................................... 87 Figure 10-7. Motorola Nonmux Write Cycle .............................................................................................................. 89 Figure 10-8. Motorola Mux Write Cycle ..................................................................................................................... 90 Figure 10-9. Serial Bus Timing Write Operation........................................................................................................ 91 Figure 10-10. Serial Bus Timing Read Operation with CLKE = 0.............................................................................. 91 Figure 10-11. Serial Bus Timing Read Operation with CLKE = 1.............................................................................. 91 Figure 10-12. Transmitter Systems Timing ............................................................................................................... 92 Figure 10-13. Receiver Systems Timing ................................................................................................................... 93 Figure 10-14. JTAG Timing ....................................................................................................................................... 94 |
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