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C8051F042-GQ Datasheet(PDF) 1 Page - Silicon Laboratories |
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C8051F042-GQ Datasheet(HTML) 1 Page - Silicon Laboratories |
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1 / 2 page  CAN 2.0B Copyright © 2005 by Silicon Laboratories 5.5.2005 UART1 SMBus SPI Bus PCA Timers 0,1,2,3,4 Internal 2% Oscillator P2.0/CPx P2.7/CPx P0.0 P0.7 DAC1 (12-Bit) VREF DAC0 (12-Bit) UART0 8:1 WDT P7 Latch P5 Latch P6 Latch P5.0/A0 P5.7/A7 P5 DRV P6.0/A8 P6.7/A15 P6 DRV P4 DRV P4.5/ALE P4.6/RD P4.7/WR P4.4 Addr [15:8] Addr [7:0] Ctrl Latch Data Latch A M U X 8:2 HVAMP TEMP SENSOR P0 Drv P1 Drv P2 Drv P3 Drv Port 0,1,2,3 &4 Latches CAN 2.0B CRX0 CTX0 8 0 5 1 C o r e Reset A M U X ADC 100 ksps (10-Bit) External Data Memory Bus 32x136 CANRAM 256 byte RAM 4 kB XRAM P3.0/AIN0.6 P3.7/AIN0.7 P1.0/AIN1.0 P1.7/AIN1.7 64 kB FLASH System Clock External Oscillator Circuit VDD Monitor C R O S S B A R Data [7:0] Address [15:0] Bus Control Digital Power Port 4 <from crossbar> A M U X ADC 500 ksps (8-Bit) VREF2 P2.1 P2.0 + - CP0 P2.3 P2.2 + - CP1 P2.5 P2.4 + - CP2 P4.0 SFR Bus P7 DRV P7.0/D0 P7.7/D7 Debug HW Boundary Scan JTAG Logic Analog Power Prog Gain Prog Gain VDD VDD VDD DGND DGND DGND RST AV+ TCK TMS TDI TDO AGND AGND AGND AV+ AV+ XTAL1 XTAL2 DAC1 AIN0.0 AIN0.1 AIN0.2 AIN0.3 DAC0 VREF MONEN VREFD VREF0 HVAIN+ HVAIN- HVREF HVCAP C8051F042 25 MIPS, 64 kB Flash, 10-Bit ADC, 100-Pin Mixed-Signal MCU Analog Peripherals 10-Bit ADC - ±1 LSB INL; guaranteed monotonic - Programmable throughput up to 100 ksps - 13 external inputs; programmable as single-ended or differential - Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5 - Data-dependent windowed interrupt generator - Built-in temperature sensor (±3 °C) High-Voltage Differential Amplifier - 60 V common mode input range - Offset adjust from –60 to +60 V - 16 gain settings from 0.05 to 16 8-Bit ADC - Programmable throughput up to 500 ksps - 8 external inputs; programmable as single-ended or differential - Programmable amplifier gain: 4, 2, 1, 0.5 Two 12-Bit DACs Three Comparators Internal Voltage Reference Precision VDD Monitor/Brown-out Detector On-Chip JTAG Debug & Boundary Scan - On-chip debug circuitry facilitates full speed, non-intrusive in-system debug (no emulator required) - Provides breakpoints, single stepping, watchpoints, stack monitor, pro- gram trace memory - Inspect/modify memory and registers - Superior performance to emulation systems using ICE-chips, target pods, and sockets - IEEE1149.1 compliant boundary scan Supply Voltage: 2.7 to 3.6 V - Typical operating current: 10 mA at 25 MHz - Multiple power saving sleep and shutdown mode Temperature Range: –40 to +85 °C High-Speed 8051 µC Core - Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks - Up to 25 MIPS throughput with 25 MHz system clock - Expanded interrupt handler Memory - 4352 bytes data RAM - 64 kB Flash; in-system programmable in 512-byte sectors (512 bytes are reserved) - External parallel data memory interface CAN Bus 2.0B - 32 message objects - ”Mailbox" implementation only interrupts CPU when needed Digital Peripherals - 64 port I/O; all are 5 V tolerant - Hardware SMBus™ (I2C™ compatible), SPI™, and two UART serial ports available concurrently - Programmable 16-bit counter array with 6 capture/compare modules - 5 general-purpose 16-bit counter/timers - Dedicated watchdog timer; bidirectional reset - Real-time clock mode using timer 3 or PCA Clock Sources - Internal programmable 2% oscillator: up to 25 MHz - External oscillator: Crystal, RC, C, or Clock Package - 100-pin TQFP (standard lead and lead-free packages Ordering Part Numbers - Lead-free package: C8051F042-GQ - Standard package: C8051F042 |
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