MX23L3254 datasheet(5/18 Pages) MCNIX

Part #	MX23L3254

Description	32M-BIT Low Voltage, Serial Mask ROM Memory with 50MHz SPI Bus Interface

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Manufacturer	MCNIX [Macronix International]

Direct Link	http://www.macronix.com

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P/N: PM1167

REV. 1.2, JUN. 08, 2005

MX23L3254

OPERATING FEATURES

Active Power, Stand-by Power

When Chip Select (S#) is Low, the device is enabled, and

in the Active Power mode. When Chip Select (S#) is High,

the device is disabled, but could remain in the Active

Power mode until all internal cycles have completed. The

device then goes in to the Stand-by Power mode. The

device consumption drops to ICC1 .

Protection Modes

The environments where non-volatile memory devices are

used can be very noisy. No SPI device can operate

correctly in the presence of excessive noise. To help

combat this, the MX23L3254 boasts the following data

protection mechanisms:

- Power-On Reset and an internal timer (tPUW) can provide

protection against inadvertant changes while the power

supply is outside the operating specification.

Hold Condition

The Hold (HOLD#) signal is used to pause any serial

communications with the device without resetting the

clocking sequence.

To enter the Hold condition, the device must be selected,

with Chip Select (S#) Low.

The Hold condition starts on the falling edge of the Hold

(HOLD) signal, provided that this coincides with Serial

Clock (C) being Low (as shown in Figure 3).

The Hold condition ends on the rising edge of the Hold

(HOLD#) signal, provided that this coincides with Serial

Clock (C) being Low.

If the falling edge does not coincide with Serial Clock (C)

being Low, the Hold condition starts after Serial Clock (C)

next goes Low. Similarly, if the rising edge does not

coincide with Serial Clock (C) being Low, the Hold condi-

tion ends after Serial Clock (C) next goes Low. (This is

shown in Figure 2).

During the Hold condition, the Serial Data Output (Q) is

high impedance, and Serial Data Input (D) and Serial Clock

(C) are Don't Care.

Normally, the device is kept selected, with Chip Select

(S#) driven Low, for the whole duration of the Hold condi-

tion. This is to ensure that the state of the internal logic

remains unchanged from the moment of entering the Hold

condition.

If Chip Select (S#) goes High while the device is in the Hold

condition, this has the effect of resetting the internal logic

of the device. To restart communication with the device,

it is necessary to drive Hold (HOLD#) High, and then to

drive Chip Select (S#) Low. This prevents the device from

going back to the Hold condition.

Figure 3. Hold Condition Activation (for data output only)

Q4

Q2

Q1

Q0

Q

C

HOLD#

C

Q0

Q1

Q3

Q4

Q5

Q2

Q3

Q2

Q5

Q6

Q

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