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TFRA84J13 Datasheet(PDF) 3 Page - Agere Systems |
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TFRA84J13 Datasheet(HTML) 3 Page - Agere Systems |
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3 / 14 page  3 3 Agere Systems Inc. TFRA84J13 Ultraframer Product Description, Revision 4 DS3/E3/DS2/E2/DS1/E1/DS0 April 29, 2005 2 Features Versatile IC supports solutions for DS3/E3, DS2/E2, DS1/J1/E1, and DS0/J0/E0 applications. Terminates up to 84 DS1/J1 or 63 E1 framed or unframed signals. All popular framing formats are sup- ported. Terminates up to three DS3/E3, 21 DS2, or 12 E2 signals. 3.3 V I/O, 1.5 V CORE, low power (<2.5 W) and –40 °C to +85 °C temperature range allows for uncontrolled or convection cooled environments. Loopbacks, manual error insertion, internal pattern generator/monitor, and internal cross connects simplify debugging and diagnostics. Standard 909-pin ball grid array (PBGA) with 35 mm square with 1.0 mm square ball pitch. Complies with all appropriate Telcordia ®, ITU, ANSI ®, ETSI, and Japanese TTC standards as noted. 2.1 Test Pattern Generator/Monitor (TPG/TPM) (x1) Configurable test pattern generator: DS1, E1, and DS2 formats. Provisionable test pattern data from the following options: quasirandom signal source (QRSS), pseudoran- dom bit stream length of 215 –1 (PRBS15), PRBS20, PRBS23, alternating 1 and 0 (ALT_01), ALL_ONES, user pattern (16 bits, repeating). The DS1 and E1 test patterns can be transmitted either unframed or as the payload of a framed signal as defined in ITU-T. Under register control, single bit or framing (DS1/E1 only) errors can be injected into any test pattern. Any sink or receiving channel can be replaced by a test pattern monitor, which can detect and count bit errors or misconfigurations, and/or detect idle conditions or AIS. Datalink (DS1-ESF DL) and SSM (E1 multiframe Sa) fields read/writable. Supports all Ultraframer modes of operation. Complies with T1.107, T1.231, T1.403, G.703, G.704, and O.150. 2.2 M13/E13 MUX (x3) 2.2.1 M13 Configurable multiplexer/demultiplexer for 28 DS1 sig- nals, 21 E1 signals, or seven DS2 signals to/from a DS3 signal. Operates in either M23 or C-bit parity mode. Provisionable time-slot selection for DS1, E1, and DS2 insertion or drop. Full alarm monitoring and generation (LOS, BPV, EXZ, OOF, SEF, AIS, RAI, FEAC, P-bit and C-bit parity errors, and FEBE). DS3 forced loopback and DS2, DS1, and E1 forced loop- back and loopback request generation. Complies with T1.102, T1.107, T1.231, T1.403, T1.404, GR 499, G.747, and G.775. 2.2.2 E13 Configurable multiplexer/demultiplexer for up to 16 E1 signals or four E2 signals, to/from an E3 signal. Independently configurable four E12 multiplexer/demulti- plexers for up to 16 E1 signals to/from four E2 signals. Provisionable time-slot selection for E1 and E2 insertion or drop via the multirate cross connect functional block. E12 and E23 multiplexers capable of generating alarm indication signal (AIS) and remote alarm indicator (RAI) signals. Configurable HDB3 encoder/decoder for E3 output/input. E1 and E2 transmit path monitors that detect loss-of- clock (LOC) and AIS. E2 receive path monitor that detects LOC, AIS, and RAI. E3 receive monitor that detects loss-of-signal (LOS), LOC, bipolar violation (BPV), AIS, and RAI. E3 and E2 loopback modes. Complies with ITU G.703, G.742, G.751, and G.775. |
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