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T8110L Datasheet(PDF) 7 Page - Agere Systems |
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T8110L Datasheet(HTML) 7 Page - Agere Systems |
7 / 164 page List of Tables Table Page Agere Systems Inc. 7 February 2004 Ambassador T8110L H.100/H.110 Switch Data Sheet Table 1. Microprocessor Interface Signals ..........................................................................................................10 Table 2. H-Bus (H.100/H.110 Interface) Signals .................................................................................................10 Table 3. L-Bus (Local) Interface Signals .............................................................................................................10 Table 4. Clock Circuit Interface Signals ..............................................................................................................11 Table 5. GPIO Interface Signals..........................................................................................................................11 Table 6. Miscellaneous Interface Signals ............................................................................................................11 Table 7. JTAG Signals ........................................................................................................................................11 Table 8. T8110L Pinouts .....................................................................................................................................13 Table 9. Intel/Motorola Protocol Selector ............................................................................................................22 Table 10. T8110L Memory Mapping to Microprocessor Space.............................................................................23 Table 11. Microprocessor Interface Register Map ................................................................................................24 Table 12. Register Space Access Timing .............................................................................................................28 Table 13. Connection Memory Space Access Timing...........................................................................................28 Table 14. Data Memory Space Access Timing .....................................................................................................29 Table 15. Control Register Map ............................................................................................................................30 Table 16. Reset Registers .....................................................................................................................................31 Table 17. Master Output Enable Register .............................................................................................................32 Table 18. Data Memory Mode Select Register .....................................................................................................32 Table 19. Clock Register Access Select Register .................................................................................................33 Table 20. Phase Alignment Select Register ..........................................................................................................33 Table 21. Fallback Control Register ......................................................................................................................34 Table 22. Fallback Type Select Register...............................................................................................................35 Table 23. Fallback Trigger Registers ....................................................................................................................35 Table 24. Watchdog Select, C8, NETREF Registers ............................................................................................36 Table 25. Watchdog EN Registers ........................................................................................................................37 Table 26. Failsafe Control Register .......................................................................................................................38 Table 27. Error and Status Register Map ..............................................................................................................39 Table 28. Clock Error Registers ............................................................................................................................40 Table 29. Latched Clock Error Registers ..............................................................................................................41 Table 30. Fallback and Failsafe Status Register ...................................................................................................42 Table 31. System Errors Registers .......................................................................................................................43 Table 32. Device Identification Registers ..............................................................................................................43 Table 33. Clock Input Control Register Map .........................................................................................................45 Table 34. Main Input Selector Register .................................................................................................................45 Table 35. Main Divider Register ............................................................................................................................46 Table 36. APLL1 Input Selector Register ..............................................................................................................46 Table 37. APLL1 Rate Register.............................................................................................................................47 Table 38. Main Inversion Select Register..............................................................................................................47 Table 39. Resource Divider Register ....................................................................................................................48 Table 40. APLL2 Rate Register.............................................................................................................................48 Table 41. LREF Input/Inversion Select Registers .................................................................................................49 Table 42. DPLL1 Input Selector Registers ............................................................................................................50 Table 43. DPLL2 Register .....................................................................................................................................51 Table 44. NETREF1 Registers ..............................................................................................................................51 Table 45. NETREF2 Registers ..............................................................................................................................52 Table 46. Clock Output Control Register Map.......................................................................................................53 Table 47. Master Output Enables Registers .........................................................................................................54 Table 48. Clock Output Format Registers .............................................................................................................55 Table 49. TCLK Select and L_SCx Select Registers ............................................................................................56 Table 50. Bit Clock and Frame ..............................................................................................................................57 |
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