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L-FW802B-DB Datasheet(PDF) 10 Page - Agere Systems |
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L-FW802B-DB Datasheet(HTML) 10 Page - Agere Systems |
10 / 26 page 10 10 Agere Systems Inc. Data Sheet, Rev. 3 May 2004 Two-Cable Transceiver/Arbiter Device FW802B Low-Power PHY IEEE 1394A-2000 37 TPBIAS0 Analog I/O Portn, Twisted-Pair Bias. (Where n refers to the port number). TPBIAS provides the 1.86 V nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers and for sending a valid cable connection signal to the remote nodes. When the FW802B’s 1394 port pins are not wired to a connector, the unused port pins may be left uncon- nected. Internal connect-detect circuitry will keep the port in a discon- nected state. 42 TPBIAS1 7, 17, 26, 27, 62 VDD — Digital Power. VDD supplies power to the digital portion of the device. 30, 31, 43, 50, 51 VDDA — Analog Circuit Power. VDDA supplies power to the analog portion of the device. 2, 14, 25, 56, 64 VSS — Digital Ground. All VSS signals should be tied to the low-impedance ground plane. 32, 49, 52, 53 VSSA — Analog Circuit Ground. All VSSA signals should be tied together to a low- impedance ground plane. 59 XI — Crystal Oscillator. XI and XO connect to a 24.576 MHz parallel resonant fundamental mode crystal. Although, when a 24.576 MHz clock source is used, it can be connected to XI with XO left unconnected. The optimum values for the external load capacitors and resistor are dependent on the specifications of the crystal used. It is necessary to add an external series resistor (RL) to the XO pin (see Figures 3 and 5). For more details, refer to the Crystal Selection Considerations section in the data sheet. Note that it is very important to place the crystal as close as possible to the XO and XI pins, i.e., within 0.5 in./1.27 cm. 60 XO Signal Information (continued) Table 1. Signal Descriptions (continued) Pin Signal* Type Name/Description * Active-low signals are indicated by “/” at the beginning of signal names, within this document. |
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