Agere Systems Inc.

9

Data Sheet, Rev. 3

May 2004

Two-Cable Transceiver/Arbiter Device

FW802B Low-Power PHY IEEE 1394A-2000

61

/RESET

I

Reset (Active-Low). When /RESET is asserted low (active), a 1394 bus

reset condition is set on the active cable ports and the FW802B is reset to

the reset start state. To guarantee that the PHY will reset, this pin must be

provided so that only an external delay capacitor (0.1

µF) and resistor

(510 k

Ω), in parallel, are required to connect this pin to ground. This

circuitry will ensure that the capacitor will be discharged when PHY power

is removed. This input is a standard logic buffer and can also be driven by

an open-drain logic output buffer. Do not leave this pin unconnected.

28

SE

I

Test Mode Control. SE is used during Agere’s manufacturing test and

29

SM

I

Test Mode Control. SM is used during Agere’s manufacturing test and

63

SYSCLK

O

System Clock. SYSCLK provides a 49.152 MHz clock signal, which is

synchronized with the data transfers to the LLC.

36

TPA0+

Analog I/O Port0, Port Cable Pair A. TPA0± is the port A connection to the twisted-

pair cable. Board traces from each pair of positive and negative differen-

tial signal pins should be kept as short as possible and matched to the

external load resistors and to the cable connector. When the FW802B’s

1394 port pins are not wired to a connector, the unused port pins may be left

unconnected. Internal connect-detect circuitry will keep the port in a discon-

nected state.

35

TPA0

−

41

TPA1

+

Analog I/O Port1, Port Cable Pair A. TPA1± is the port A connection to the twisted-

pair cable. Board traces from each pair of positive and negative differen-

tial signal pins should be kept as short as possible and matched to the

external load resistors and to the cable connector. When the FW802B’s

1394 port pins are not wired to a connector, the unused port pins may be

left unconnected. Internal connect-detect circuitry will keep the port in a

disconnected state.

40

TPA1

−

34

TPB0+

Analog I/O Port0, Port Cable Pair B. TPB0± is the port B connection to the twisted-

pair cable. Board traces from each pair of positive and negative differen-

tial signal pins should be kept as short as possible and matched to the

external load resistors and to the cable connector. When the FW802B’s

1394 port pins are not wired to a connector, the unused port pins may be

left unconnected. Internal connect-detect circuitry will keep the port in a

disconnected state.

33

TPB0

−

39

TPB1

+

Analog I/O Port1, Port Cable Pair B. TPB1± is the port B connection to the twisted-

pair cable. Board traces from each pair of positive and negative differen-

tial signal pins should be kept as short as possible and matched to the

external load resistors and to the cable connector. When the FW802B’s

1394 port pins are not wired to a connector, the unused port pins may be

left unconnected. Internal connect-detect circuitry will keep the port in a

disconnected state.

38

TPB1

−

Table 1. Signal Descriptions (continued)

Pin

Signal*

Type

Name/Description

* Active-low signals are indicated by “/” at the beginning of signal names, within this document.