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DSP16411 Datasheet(PDF) 3 Page - Agere Systems |
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DSP16411 Datasheet(HTML) 3 Page - Agere Systems |
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3 / 316 page  Table of Contents (continued) Contents Page Data Sheet May 2003 DSP16411 Digital Signal Processor Agere Systems Inc. Agere Systems—Proprietary 3 Use pursuant to Company instructions " 4.6.1 Private Internal Memory..............................................................................................................43 " 4.6.2 Shared Internal I/O......................................................................................................................43 " 4.6.3 Shared External I/O and Memory................................................................................................43 " 4.6.4 X-Memory Map ...........................................................................................................................44 " 4.6.5 Y-Memory Maps ..........................................................................................................................45 " 4.6.6 Z-Memory Maps..........................................................................................................................46 " 4.6.7 Internal I/O Detailed Memory Map ..............................................................................................47 " 4.7 Triport Random-Access Memory (TPRAM) ..........................................................................................48 " 4.8 Shared Local Memory (SLM)................................................................................................................49 " 4.9 Bit Input/Output Units (BIO 〈0—1〉) .......................................................................................................50 " 4.10 Timer Units (TIMER0_ 〈0—1〉 and TIMER1_〈0—1〉) ............................................................................53 " 4.11 Hardware Development System (HDS 〈0—1〉) .....................................................................................56 " 4.12 JTAG Test Port (JTAG 〈0—1〉)...............................................................................................................57 " 4.12.1 Port Identification ........................................................................................................................57 " 4.12.2 Emulation Interface Signals to the DSP16411 ............................................................................58 " 4.12.2.1 TCS 14-Pin Header.....................................................................................................58 " 4.12.2.2 JCS 20-Pin Header .....................................................................................................59 " 4.12.2.3 HDS 9-Pin, D-Type Connector....................................................................................60 " 4.12.3 Multiprocessor JTAG Connections..............................................................................................61 " 4.12.4 Boundary Scan ...........................................................................................................................62 " 4.13 Direct Memory Access Unit (DMAU).....................................................................................................64 " 4.13.1 Overview .....................................................................................................................................64 " 4.13.2 Registers.....................................................................................................................................67 " 4.13.3 Data Structures ...........................................................................................................................83 " 4.13.3.1 One-Dimensional Data Structure (SWT Channels).....................................................83 " 4.13.3.2 Two-Dimensional Data Structure (SWT Channels).....................................................84 " 4.13.3.3 Memory-to-Memory Block Transfers (MMT Channels) ...............................................86 " 4.13.4 The PIU Addressing Bypass Channel.........................................................................................86 " 4.13.5 Single-Word Transfer Channels (SWT).......................................................................................87 " 4.13.6 Memory-to-Memory Transfer Channels (MMT)...........................................................................90 " 4.13.7 Interrupts and Priority Resolution................................................................................................92 " 4.13.8 Error Reporting and Recovery ....................................................................................................94 " 4.13.9 Programming Examples..............................................................................................................95 " 4.13.9.1 SWT Example 1: A Two-Dimensional Array ...............................................................95 " 4.13.9.2 SWT Example 2: A One-Dimensional Array ...............................................................97 " 4.13.9.3 MMT Example.............................................................................................................99 " 4.14 System and External Memory Interface (SEMI)..................................................................................100 " 4.14.1 External Interface......................................................................................................................101 " 4.14.1.1 Configuration.............................................................................................................102 " 4.14.1.2 Asynchronous Memory Bus Arbitration.....................................................................103 " 4.14.1.3 Enables and Strobes.................................................................................................104 " 4.14.1.4 External Clock...........................................................................................................105 " 4.14.1.5 Address and Data .....................................................................................................106 " 4.14.2 16-Bit External Bus Accesses...................................................................................................109 " 4.14.3 32-Bit External Bus Accesses...................................................................................................109 " 4.14.4 Registers................................................................................................................................... 110 " 4.14.4.1 ECON0 Register ....................................................................................................... 111 " 4.14.4.2 ECON1 Register ....................................................................................................... 112 " 4.14.4.3 Segment Registers ................................................................................................... 114 " 4.14.5 Asynchronous Memory ............................................................................................................. 116 " 4.14.5.1 Functional Timing...................................................................................................... 116 |
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