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LTC4060EDHC Datasheet(PDF) 4 Page - Linear Integrated Systems

Part # LTC4060EDHC
Description  Standalone Linear NiMH/NiCd Fast Battery Charger
Download  20 Pages
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Manufacturer  LINEAR [Linear Integrated Systems]
Direct Link  http://www.linearsystems.com
Logo LINEAR - Linear Integrated Systems

LTC4060EDHC Datasheet(HTML) 4 Page - Linear Integrated Systems

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4
LTC4060
4060f
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
The
indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VBAT = 2.8V, GND = 0V unless otherwise specified. All
currents into the device pins are positive and all currents out of the device pins are negative. All voltages are referenced to GND
unless otherwise specified.
ELECTRICAL CHARACTERISTICS
VHTIH
NTC Pin Hot Charge Initiation Hysteresis Voltage
VNTC Increasing
100
mV
VHTC
NTC Pin Hot Charge Cutoff Threshold Voltage
VNTC Decreasing, 4.5V ≤ VCC ≤ 10V
0.37 •
0.4 •
0.43 •
V
VCC
VCC
VCC
VHTCH
NTC Pin Hot Charge Cutoff Hysteresis Voltage
VNTC Increasing
100
mV
VNDIS
NTC Pin Disable Threshold Voltage
25
250
mV
INL
NTC Pin Pull-Down Current
VNTC = 2.5V
0.15
1.5
µA
tACC
Timer Accuracy
RPROG = 698Ω, CTIMER = 1.2nF and
–15
0
15
%
RPROG = 3480Ω, CTIMER = 470pF
Output Drivers
IDRV
Drive Pin Sink Current
VDRIVE = 4V
40
70
120
mA
RDRV
Drive Pin Resistance to VCC
VDRIVE = 4V, Not Charging
4700
VOL
ACP, CHRG Output Pins Low Voltage
IACP = ICHRG = 10mA
0.8
V
IOH
ACP, CHRG Output Pins High Leakage Current
Outputs Inactive, VCHRG = VACP = VCC
–2
2
µA
Control Inputs
VIT
SHDN, SEL0, SEL1, CHEM, PAUSE Pins Digital
VCC = 10V
350
650
mV
Input Threshold Voltage
VITH
SHDN, SEL0, SEL1, CHEM, PAUSE Pins Digital
50
mV
Input Hysteresis Voltage
IIPD
SHDN, SEL0, SEL1, CHEM Pins Digital Input
VCC = 10V, VIN = VCC
0.4
2
µA
Pull-Down Current
IIPU
PAUSE Pin Digital Input Pull-Up Current
VIN = GND
–2
–0.4
µA
Note 1: Absolute Maximum Ratings only indicate limits for survivability.
Operating the device beyond these limits may result in permanent damage.
Continuous or extended application of these maximum levels may
adversely affect device reliability.
Note 2: The LTC4060 is guaranteed to meet performance specifications
from 0°C to 70°C ambient temperature range and 0°C to 85°C junction
temperature range. Specifications over the –40°C to 85°C operating
ambient temperature range are assured by design, characterization and
correlation with statistical process controls.
Note 3: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Overtempera-
ture protection is activated at a temperature of approximately 145°C,
which is above the specified maximum operating junction temperature.
Continuous operation above the specified maximum operation temperature
may result in device degradation or failure. Operating junction temperature
TJ (in °C) is calculated from the ambient temperature TA and the average
power dissipation PD (in watts) by the formula:
TJ = TA + θJA • PD
Note 4: Short duration drops below the minimum VCC specification of
several microseconds or less are ignored by the undervoltage detection
circuit.
Note 5: Assumes that the external PNP pass transistor has negligible B-C
reverse leakage current when the collector is biased at 2.8V (VBAT for two
charged cells in series) and the base is biased at VCC.
Note 6: Assumes that the external PNP pass transistor has negligible B-E
reverse leakage current when the emitter is biased at 0V (VCC) and the
base is biased at 5.6V (VBAT for four charged cells in series).
Note 7: The charge current specified is the regulated current through the
internal current sense resistor that flows into the external PNP pass
transistor’s emitter. Actual battery charging current is slightly less and
depends upon PNP alpha.
Note 8: Given as a per cell voltage (VBAT/Number of Cells).
Note 9: Supply current includes the current programming resistor current
of 2mA. The charger is paused and not charging the battery.
Note 10: The minimum VCC supply is set at 5V during this test to
compensate for voltage drops due to test socket contact resistance and 2A
of current. This ensures that the supply voltage delivered to the device
under test does not fall below the UVLO entry threshold. Specification at
the minimum VCC of 4.5V is assured by design and characterization.


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