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GS9020ACTV Datasheet(PDF) 8 Page - Gennum Corporation |
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GS9020ACTV Datasheet(HTML) 8 Page - Gennum Corporation |
8 / 31 page 19922 - 3 8 of 31 DETAILED DESCRIPTION The GS9020A EDH coprocessor consists of five major blocks: 1. Data Input/Output Block (with automatic standard detect) 2. Flywheel Block 3. EDH Block 4. Data Processing Block 5. Host Interface (HOSTIF) Block The following convention is used to differentiate device pins from HOST interface table bits. LOGIC OPR (logic operator) gives the combinational relationship (if one exists), between pins which also have a corresponding HOST bit. This operator governs the signal the GS9020A receives. The following is the list of possible logic operators and their meaning. 1. DATA INPUT/OUTPUT BLOCK 1.1 Serial Video Data Inputs Serial data and clock signals are supplied to the GS9020A chip via the SDI/SDI and SCI/SCI pins, respectively. Eight standards are supported: Composite, 4:2:2 Component with 13.5MHz Y sampling, 4:2:2 16 x 9 wide screen with 18MHz Y sampling, and 4:4:4:4 Component Single Link with 13.5MHz Y sampling, all in both NTSC and PAL formats. See Table 1. SDI/SDI and SCI/SCI are high speed Pseudo-ECL (PECL) compatible differential inputs with internal pullup resistors (75 Ω nominally) as shown in Figure 4. Note that each pullup resistor has a dedicated power pin allowing the use of other interfacing topologies. The internal pullup resistors allow the GS9020A to be easily interfaced to the GS9025A as shown in Figure 5 and Figure 17. An external diode is required to offset the input signals to the input range of the GS9020A. For maximum signal integrity the GS9025A and GS9020A should be placed as close together as possible. The PECL serial input signals are first converted to CMOS levels and then deserialized to 10 bit parallel format (based on the TRS headers), descrambled, and then passed to the processing core. 1.2 Parallel Digital Video Data Outputs The output of the device is 10-bit digital video data and is present on the DOUT[9:0] output pins. 1.3 Reserialized Data Output The GS9020A also provides PECL differential serial data outputs (SDO/SDO). The serial data outputs can operate in one of two modes as controlled by the SDOMODE pin. When SDOMODE is set LOW, re-serialized processed data is output at the SDO/SDO output pins. In this mode it is recommended that the lock output of the GS9025A or GS9035A connected to the RESET input of the GS9020A, and to a pull up resistor. This will effectively reset the GS9020A whenever the signal lock is lost. Note that any GS9020A programming through the host interface will be lost after this reset. It will be necessary to reprogram the GS9020A after each reset. When SDOMODE is set HIGH, the serial input data is supplied directly to the SDO/SDO output pins, bypassing the processing core. After changing SDOMODE, the GS9020A must be reset for proper operation. PIN LOGIC OPR HOSTIF XX YY LOGIC OPR MEANING AND XX AND YY OR XX OR YY > XX takes precedence over YY < YY takes precedence over XX PIN LOGIC OPR HOST BIT SDI, SDI SCI, SCI PIN LOGIC OPR HOST BIT DOUT[9:0] PIN LOGIC OPR HOST BIT SDO, SDO SDOMODE |
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