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GS1532-CFE3 Datasheet(PDF) 10 Page - Gennum Corporation |
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GS1532-CFE3 Datasheet(HTML) 10 Page - Gennum Corporation |
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10 / 52 page  GS1532 Data Sheet 21498 - 6 June 2005 10 of 52 35 V Synchronous with PCLK Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to indicate the portion of the video field / frame that is used for vertical blanking when DETECT_TRS is set LOW. The device will set the V bit in all outgoing TRS signals for the entire period that the V input signal is HIGH (IOPROC_EN/DIS must also be HIGH). The V signal should be set HIGH for the entire vertical blanking period and should be set LOW for all lines outside of the vertical blanking interval. The V signal is ignored when DETECT_TRS = HIGH. 36 H Synchronous with PCLK Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to indicate the portion of the video line containing active video data when DETECT_TRS is set LOW. The device will set the H bit in all outgoing TRS signals for the entire period that the H input signal is HIGH (IOPROC_EN/DIS must also be HIGH). H signal timing is configurable via the H_CONFIG bit of the IOPROC_DISABLE register, accessible via the host interface. Active Line Blanking (H_CONFIG = 0h) The H signal should be set HIGH for the entire horizontal blanking period, including the EAV and SAV TRS words, and LOW otherwise. This is the default setting. TRS Based Blanking (H_CONFIG = 1h) The H signal should be set HIGH for the entire horizontal blanking period as indicated by the H bit in the received TRS ID words, and LOW otherwise. 37, 64 CORE_VDD – Power Power supply connection for the digital core logic. Connect to +1.8V DC digital. Table 1-1: Pin Descriptions (Continued) Pin Number Name Timing Type Description |
Similar Part No. - GS1532-CFE3 |
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Similar Description - GS1532-CFE3 |
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