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Military 5.0V pASIC 1 Family
QL12x16B
AC CHARACTERISTICS at VCC = 5V, TA = 25
°C (K = 1.00)
Logic Cell
Input Cells
Output Cell
Notes:
[6] See High Drive Buffer Table for more information.
[7] Clock buffer fanout refers to the maximum number of flip flops per half column. The number of half col-
umns used does not affect clock buffer delay.
[8] The following loads are used for tPXZ:
QL12X16B
Propagation Delays (ns)
Symbol
Parameter
Fanout
12
348
tPD
Combinatorial Delay [5]
1.7
2.2
2.6
3.2
5.2
tSU
Setup Time [5]
2.1
2.1
2.1
2.1
2.1
tH
Hold Time
0.0
0.0
0.0
0.0
0.0
tCLK
Clock to Q Delay
1.0
1.5
1.9
2.5
4.6
tCWHI
Clock High Time
2.0
2.0
2.0
2.0
2.0
tCWLO
Clock Low Time
2.0
2.0
2.0
2.0
2.0
tSET
Set Delay
1.7
2.1
2.6
3.2
5.2
tRESET
Reset Delay
1.5
1.9
2.2
2.7
4.3
tSW
Set Width
1.9
1.9
1.9
1.9
1.9
tRW
Reset Width
1.8
1.8
1.8
1.8
1.8
Symbol
Parameter
Propagation Delays (ns) [4]
12346
8
tIN
High Drive Input Delay [6]
2.4
2.5
2.6
2.7
3.0
3.3
tINI
High Drive Input, Inverting Delay [6]
2.5
2.6
2.7
2.8
3.1
3.4
tIO
Input Delay (bidirectional pad)
1.4
1.9
2.2
2.8
3.7
4.6
tGCK
Clock Buffer Delay [7]
2.7
2.8
2.8
2.9
2.9
3.0
tGCKHI
Clock Buffer Min High [7]
2.0
2.0
2.0
2.0
2.0
2.0
tGCKLO
Clock Buffer Min Low [7]
2.0
2.0
2.0
2.0
2.0
2.0
Propagation Delays (ns) [4]
Symbol
Parameter
Output Load Capacitance (pF)
30
50
75
100
150
tOUTLH
Output Delay Low to High
2.7
3.4
4.2
5.0
6.7
tOUTHL
Output Delay High to Low
2.8
3.7
4.7
5.6
7.6
tPZH
Output Delay Tri-state to High
4.0
4.9
6.1
7.3
9.7
tPZL
Output Delay Tri-state to Low
3.6
4.2
5.0
5.8
7.3
tPHZ
Output Delay High to Tri-state [8]
2.9
tPLZ
Output Delay Low to Tri-state [8]
3.3
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