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HYB39S64800CTL Datasheet(PDF) 2 Page - Infineon Technologies AG |
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HYB39S64800CTL Datasheet(HTML) 2 Page - Infineon Technologies AG |
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2 / 52 page  HYB 39S64400/800CT(L) 64-MBit Synchronous DRAM Data Book 2 12.99 Ordering Information Type Ordering Code Package Description HYB 39S64400CT-7.5 PC133-333 P-TSOP-54-2 (400mil) 133 MHz 4B × 4M x4 SDRAM HYB 39S64400CT-8 PC100-222 P-TSOP-54-2 (400mil) 125 MHz 4B × 4M x4 SDRAM HYB 39S64800CT-7.5 PC133-333 P-TSOP-54-2 (400mil) 133 MHz 4B × 2M x8 SDRAM HYB 39S64800CT-8 PC100-222 P-TSOP-54-2 (400mil) 125 MHz 4B × 2M x8 SDRAM HYB 39S64xxx0CTL-8 PC100-222 P-TSOP-54-2 (400mil) Low Power (L-versions) Pin Definitions and Functions CLK Clock Input DQ Data Input/Output CKE Clock Enable DQM Data Mask CS Chip Select V DD Power (+ 3.3 V) RAS Row Address Strobe V SS Ground CAS Column Address Strobe V DDQ Power for DQ’s (+ 3.3 V) WE Write Enable V SSQ Ground for DQ’s A0 - A11 Address Inputs N.C. Not connected BA0, BA1 Bank Select |
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