3

MB15F74UV

Aug. 2003

Edition 0.2

PIN DESCRIPTIONS

Pin No.

Pin

name

I/O

Descriptions

1

GND

-

Ground for OSC input buffer and the shift registor circuit.

I

Prescaler input pin for the IF-PLL section.

Connection to an external VCO should be AC coupling.

I

Prescaler complimentary input for the IF-PLL section.

This pin should be grounded via a capacitor.

-

Ground for the IF-PLL section.

-

Power supply voltage input pin for the IF-PLL section(except for the

charge pump circuit), the shift register and the oscillator input buffer.

When power is OFF, latched data of IF-PLL is lost.

O

Charge pump output for the IF-PLL section.

Phase characteristics of the phase detector can be reversed by FC-bit.

I

Power saving mode control for the IF-PLL section. This pin must be set

at ”L” Power-ON. (Open is prohibited.)

8LD/fout

O

Lock detect signal output(LD)/ phase comparator monitoring outut

(fout). The output signal is selected by a LDS bit in a serial data.

LDS bit = "1" ; outputs fout signal LDS bit = "0" ; outputs LD sihnal

I

Power saving mode control for the RF-PLL section. This pin must be

set at ”L” Power-ON. (Open is prohibited.)

10

O

Charge pump output for the RF-PLL section.

Phase characteristics of the phase detector can be reversed by FC-bit.

11

-

Power supply voltage input pin for the RF-PLL section(except for the

charge pump circuit).

12

-

Ground for the RF-PLL section.

13

I

Prescaler complimentary input for the RF-PLL section.

This pin should be grounded via a capacitor.

14

I

Prescaler input pin for the RF-PLL.

Connction to an external VCO should be AC coupling.

15

LE

I

Load enable signal input (with the schmitt trigger circuit.)

When LE is set "H", data in the shift register is transferred to the corre-

sponding latch according to the control bit in a serial data.

16

Data

I

Serial data input (with the schmitt trigger circuit.)

A data is transferred to the corresponding latch (IF-ref counter, IF-prog.

counter, RF-ref. counter, RF-prog. counter) according to the control bit

in a serial data.

17

Clock

I

Clock input for the 23-bit shift register (with the schmitt trigger circuit.)

One bit data is shifted into the shift register on a rising edge of the

clock.

18

I

The programmable reference divider input. TCXO should be connected

with a AC coupling capacitor.