8

MB15F74UV

Aug. 2003

Edition 0.2

FUNCTIONAL DESCRIPTIONS

The divide ratio can be calculated using the following equation:

÷ R

Output frequency of external voltage controlled oscillator (VCO)

P:

Preset divide ratio of dual modulus prescaler (32 or 64 for IF-PLL, 64 or 128 for RF-PLL)

N:

Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)

A:

Preset divide ratio of binary 7-bit swallow counter (0

≤ A ≤ 127, condition;A < N)

Reference oscillation frequency

R:

Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)

Serial Data Input

Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-PLL

sections, programmable reference dividers of IF/RF-PLL sections are controlled individually.

Serial data of binary data is entered through Data pin.

On a rising edge of clock, one bit of serial data is transferred into the shift register. On a rising edge of load enable

signal , the data stored in the shift register is transferred to one of latch of them depending upon the control bit data

setting.

Table1. Control Bit

Shift Register Configuration

Control bit

Destination of serial data

CN1

CN2

00

The programmable reference counter for the IF-PLL.

10

The programmable reference counter for the RF-PLL.

01

The programmable counter and the swallow counter for the IF-PLL

11

The programmable counter and the swallow counter for the RF-PLL

Programmable Reference Counter

C

N

1

1

2

T

1

3

R

1

4

R

2

5

R

3

6

R

4

7

R

5

8

R

6

9

R

7

10

R

8

11

R

9

12

R

10

13

R

11

14

R

12

15

R

13

16

R

14

17

LSB

MSB

Data Flow

C

N

2

T

2

18

CN1, 2

: Control bit

[Table. 1]

R1 to R14

: Divide ratio setting bits for the programmable reference counter (3 to 16,383)

[Table. 2]

T1, 2

: LD/fout output setting bit

[Table. 3]

CS

: Charge pump current select bit

[Table. 8]

X

: Dummy bits(Set "0" or "1")

NOTE: Data input with MSB first.

19

20

21

22

23

C

S

X

X

X

X