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NTHC5513T1G Datasheet(PDF) 8 Page - ON Semiconductor |
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NTHC5513T1G Datasheet(HTML) 8 Page - ON Semiconductor |
8 / 10 page NTHC5513 http://onsemi.com 8 Figure 22. Basic Figure 23. Style 2 0.457 0.018 2.032 0.08 0.635 0.025 0.66 0.026 0.711 0.028 0.457 0.018 2.032 0.08 0.635 0.025 0.66 0.026 0.254 0.010 1.092 0.043 0.178 0.007 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* BASIC PAD PATTERNS The basic pad layout with dimensions is shown in Figure 22. This is sufficient for low power dissipation MOSFET applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. The minimum recommended pad pattern shown in Figure 23 improves the thermal area of the drain connections (pins 5, 6, 7, 8) while remaining within the confines of the basic footprint. The drain copper area is 0.0019 sq. in. (or 1.22 sq. mm). This will assist the power dissipation path away from the device (through the copper lead−frame) and into the board and exterior chassis (if applicable) for the single device. The addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further. |
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