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WM8781 Datasheet(PDF) 9 Page - Wolfson Microelectronics plc |
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WM8781 Datasheet(HTML) 9 Page - Wolfson Microelectronics plc |
9 / 20 page Production Data WM8781 w PD, April 2006, Rev 4.1 9 AUDIO INTERFACE TIMING – SLAVE MODE Figure 3 Digital Audio Data Timing – Slave Mode Test Conditions DVDD = 3.3V, DGND = 0V, TA = +25 oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Input Timing Information BCLK cycle time tBCY 50 ns BCLK pulse width high tBCH 20 ns BCLK pulse width low tBCL 20 ns LRCLK set-up time to BCLK rising edge tLRSU 10 ns LRCLK hold time from BCLK rising edge tLRH 10 ns DOUT propagation delay from BCLK falling edge tDD 0 10 ns Table 3 Digital Audio Data Timing - Slave Mode Note: LRCLK should be synchronous with MCLK, although the WM8781 interface is tolerant of phase variations or jitter on these signals. |
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