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TPS65560RGTRG4 Datasheet(PDF) 2 Page - Texas Instruments |
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TPS65560RGTRG4 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 13 page www.ti.com ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS DISSIPATION RATINGS TPS65560 SLVS608 – JANUARY 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TA PACKAGE MARKING PACKAGE(1) PART NUMBER -35 °C to 85°C BPR 16-pin QFN TPS65560RGT (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. over operating free-air temperature range (unless otherwise noted) (1) UNIT VCC -0.6 V to 6 V VSS Supply voltage VBAT -0.6 V to 13 V V(SW) Switch terminal voltage -0.6 V to 50 V I(SW) Switch current between SW and PGND, ISW 3 A VI Input voltage of CHG, I_PEAK, F_ON -0.3 V to VCC Tstg Storage temperature -40 °C to 150°C TJ Maximum junction temperature 125 °C ESD rating HBM (Human Body Model) JEDEC JES22-A114 1 kV (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. MIN NOM MAX UNIT Supply voltage, VCC 2.7 4 V VSS Supply voltage, VBAT 1.6 12 V V(SW) Switch terminal voltage, -0.3 45 V I(SW) Switch current between SW and PGND 2 A Operating free-air temperature range -35 85 °C VIH High-level digital input voltage at CHG and F_ON 2 V VIL Low-level digital input voltage at CHG and F_ON 0.5 V POWER RATING POWER RATING POWER RATING PACKAGE RθJA (1) TA < 25°C TA = 70°C TA = 85°C QFN 47.4 °C/W 2.11 W 1.16 W 844 mW (1) The thermal resistance, RθJA, is based on a soldered PowerPAD™ on a 2S2P JEDEC board using thermal vias. 2 Submit Documentation Feedback |
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