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TC58NVG1S3BFT00 Datasheet(PDF) 5 Page - Toshiba Semiconductor

Part # TC58NVG1S3BFT00
Description  TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TC58NVG1S3BFT00 Datasheet(HTML) 5 Page - Toshiba Semiconductor

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TC58NVG1S3BFT00/TC58NVG1S8BFT00
2003-10-30A
5
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta
= 0 to 70℃, VCC = 2.7 V to 3.6 V)
SYMBOL
PARAMETER
MIN
MAX
UNIT
NOTES
tCLS
CLE Setup Time
0
ns
tCLH
CLE Hold Time
10
ns
tCS
CE Setup Time
0
ns
tCH
CE Hold Time
10
ns
tWP
Write Pulse Width
25
ns
tALS
ALE Setup Time
0
ns
tALH
ALE Hold Time
10
ns
tDS
Data Setup Time
20
ns
tDH
Data Hold Time
10
ns
tWC
Write Cycle Time
50
ns
tWH
WE High Hold Time
15
ns
tWW
WP High to WE Low
100
ns
tRR
Ready to RE Falling Edge
20
ns
tRW
Ready to WE Falling Edge
20
ns
tRP
Read Pulse Width
35
ns
tRC
Read Cycle Time
50
ns
tREA
RE Access Time
35
ns
tCEA
CE Access Time
45
ns
tCLEA
CLE Access Time
45
ns
tALEA
ALE Access Time
45
ns
tOH
Data Output Hold Time
10
ns
tRHZ
RE High to Output High Impedance
30
ns
tCHZ
CE High to Output High Impedance
20
ns
tREH
RE High Hold Time
15
ns
tIR
Output-High-impedance-to- RE Falling Edge
0
ns
tRHW
RE High to WE Low
30
ns
tWHC
WE High to CE Low
30
ns
tWHR
WE High to RE Low
30
ns
tR
Memory Cell Array to Starting Address
25
µs
tWB
WE High to Busy
200
ns
tRST
Device Reset Time (Ready/Read/Program/Erase)
6/6/10/500
µs


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