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DS15MB200 Datasheet(PDF) 6 Page - National Semiconductor (TI) |
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DS15MB200 Datasheet(HTML) 6 Page - National Semiconductor (TI) |
6 / 10 page Electrical Characteristics (Continued) Over recommended operating supply and temperature ranges unless other specified. Symbol Parameter Conditions Min Typ (Note 8) Max Units SUPPLY CURRENT (Static) I CC Supply Current All inputs and outputs enabled and active, terminated with external load of 100 Ω between OUT+ and OUT-. 225 275 mA I CCZ Supply Current - Powerdown Mode ENA_0 = ENB_0 = ENL_0 = ENA_1 = ENB_1 = ENL_1 = L 0.6 4.0 SWITCHING CHARACTERISTICS — LVDS OUTPUTS t LHT Differential Low to High Transition Time Use an alternating 1 and 0 pattern at 200 Mb/s, measure between 20% and 80% of V OD. 170 250 ps t HLT Differential High to Low Transition Time 170 250 ps t PLHD Differential Low to High Propagation Delay Use an alternating 1 and 0 pattern at 200 Mb/s, measure at 50% V OD between input to output. 1.0 2.5 ns t PHLD Differential High to Low Propagation Delay 1.0 2.5 ns t SKD1 Pulse Skew |t PLHD–tPHLD|25 75 ps t SKCC Output Channel to Channel Skew Difference in propagation delay (t PLHD or t PHLD) among all output channels. 50 115 ps t JIT Jitter (0% Pre-emphasis) (Note 11) RJ - Alternating 1 and 0 at 750MHz (Note 12) 1.1 1.5 psrms DJ - K28.5 Pattern, 1.5 Gbps (Note 13) 20 34 psp-p TJ - PRBS 2 7-1 Pattern, 1.5 Gbps (Note 14) 14 28 psp-p t ON LVDS Output Enable Time Time from ENA_n, ENB_n, or ENL_n to OUT± change from TRI-STATE to active. 0.5 1.5 µs t ON2 LVDS Output Enable Time from Powerdown Mode Time from ENA_n, ENB_n, or ENL_n to OUT± change from Powerdown Mode to active. 10 20 µs t OFF LVDS Output Disable Time Time from ENA_n, ENB_n, or ENL_n to OUT± change from active to TRI-STATE or Powerdown mode. 12 ns Note 8: Typical parameters are measured at VDD = 3.3V, TA = 25˚C. They are for reference purposes, and are not production-tested. Note 9: Differential output voltage VOD is defined as ABS(OUT+–OUT−). Differential input voltage VID is defined as ABS(IN+–IN−). Note 10: Output offset voltage VOS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states. Note 11: Jitter is not production tested, but guaranteed through characterization on a sample basis. Note 12: Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = VID = 500mV, 50% duty cycle at 750MHz, tr =tf = 50ps (20% to 80%). Note 13: Deterministic Jitter, or DJ, is measured to a histogram mean with a sample size of 350 hits. Stimulus and fixture jitter have been subtracted. The input voltage = VID = 500mV, K28.5 pattern at 1.5 Gbps, tr =tf = 50ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101). Note 14: Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture jitter have been subtracted. The input voltage =VID = 500mV, 2 7-1 PRBS pattern at 1.5 Gbps, t r =tf = 50ps (20% to 80%). www.national.com 6 |
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