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CM8500A
3A BUS TERMINATOR
CM8500ATEVAL PCB LAYOUT
Figure 4. CM8500AEVAL PCB Layout
SSTL-2 SPECIFICATIONS
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
VDD
Device Supply Voltage
VDDQ
N/A
V
VDDQ
Output Supply Voltage
2.3
2.5
2.7
V
VREF
Input Reference Voltage
1.15
1.25
1.35
V
VTT
Termination Voltage
VREF - 0.04
VREF
VREF + 0.04
V
INPUT DC LOGIC LEVELS
VIH (DC)
DC Input Logic High
VREF + 0.18
VDDQ + 0.3
V
VIL (DC)
DC Input Logic Low
- 0.3
VREF - 0.18
V
INPUT AC LOGIC LEVELS
VIH (AC)
AC Input Logic High
VREF + 0.35
V
VIL (AC)
AC Input Logic Low
VREF - 0.35
V
OUTPUT DC CURRENT DRIVE
IOH (DC)
Output Minimum Source DC Current
- 15.2
mA
IOL (DC)
Output Minimum Sink DC Current
15.2
mA
Notes:
VREF and VTT must track variations in VDDQ
Peak-to-peak AC noise on VREF may not exceed ±2% VREF (DC)
VTT of transmitting device must track VREF of receiving device
Table 1. Key Specifications for SSTL_2
2004/12/20
Champion Microelectronic Corporation
Page 8
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