U2784B-BFSG3 datasheet(4/11 Pages) TEMIC

Part #	U2784B-BFSG3

Description	2200 MHz / 200 MHz Twin PLL

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Manufacturer	TEMIC [TEMIC Semiconductors]

Direct Link	http://www.temic.de

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U2784B

TELEFUNKEN Semiconductors

Rev. A2, 29-Jul-96

4 (11)

Serial Programming Bus

Reference

and

programmable

counters

can

be

programmed by the 3-wire-bus (Clock, Data and Enable).

After setting enable signal to high condition, the data

status is transfered bit by bit on the rising edge of the clock

signal into the shift register, starting with the MSB-bit.

After the Enable signal returns to low condition the

programmed information is loaded according to the

addressbits (last three bits) into the addressed latch.

Additional leading bits are ignored and there is no check

made the 3-wire-bus remains active and the IC can be

programmed.

Data is entered with the most significant bit first. The

leading bits deliver the divider or control information.

The trailing three bits are the address field. There are six

different addresses used. The trailing address bits are

decoded upon the falling edge of the Enable signal. the

internal Loadpulse is beginning with the falling edge of

the Enable signal and ending with the falling edge of the

Clock

signal.

Therefore

a

minimum

holdtime

clock-enable tHCE is required.

Bit Allocation

MSB

LSB

Bit

1

Bit

2

Bit

3

Bit

4

Bit

5

Bit

6

Bit

7

Bit

8

Bit

9

Bit

10

Bit

11

Bit

12

Bit

13

Bit

14

Bit

15

Bit

16

Bit

17

Bit

18

Bit

19

Bit

20

data bits

address bits

D16 D15 D14 D13 D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

A2

A1

A0

PLL1

M10

M9

M8

M7

M6

M5

M4

M3

M2

M1

M0

S5

S4

S3

S2

S1

PLL1

S0

0

1

PLL1

R11

R10

R9

R8

R7

R6

R5

R4

R3

R2

R1

PLL1

R0

0

1

0

PLL2

M10

M9

M8

M7

M6

M5

M4

M3

M2

M1

M0

S2

S1

PLL2

S0

0

1

PLL2

R11

R10

R9

R8

R7

R6

R5

R4

R3

R2

R1

PLL2

R0

1

0

RF/

2

Test

5IP

TRI

2

TRI

1

PS2

PS1

H2P H1P

LP

B

LPA

P4

P3

P2

P1

P0

1

0

1

SP

D 5I

SP

D 2

SP

D 1

1

0

Scaling Factors

PGD of PLL1:

S0 ... S5:

These bits are setting the swallow counter SS.

SS = S0*20 + S1*21 + ... + S4*24 + S5*25

allowed scalling factors for SS: 0 ... 63, SS < SM

M0 ... M10: These bits are setting the main counter SM.

SM = M0*20 + M1*21 + ... + M9*29 + M10*210

allowed scalling factors for SM: 5 ... 2047

SPGD:

Total scalling factor of the programmable counter:

SPGD = (64*SM) + SS

Condition: SS < SM

RFD of PLL1 and PLL2:

R0 ... R11:

These bits are setting the reference counter SR.

SR = R0*20 + ... + R10*210 + R11*211

allowed scalling factors for SR: 5 ... 4095

RF/2 = 1:

SRFD = 2 * SR

RF/2 = 0:

SRFD = SR

PGD of PLL2:

S0 ... S4:

These bits are setting the swallow counter SS.

SS = S0*20 + S1*21 + S2*22

allowed scalling factors for SS: 0 ... 7, SS < SM

M0 ... M9:

These bits are setting the main counter SM.

SM = M0*20 + M1*21 + ... + M9*29 + M10*210

allowed scalling factors for SM: 5 ... 2047

SPGD:

Total scalling factor of the programmable counter:

SPGD = (8*SM) + SS

Condition: SS < SM

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