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M5M5V408BTP-85LW Datasheet(PDF) 7 Page - Mitsubishi Electric Semiconductor |
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M5M5V408BTP-85LW Datasheet(HTML) 7 Page - Mitsubishi Electric Semiconductor |
7 / 14 page MITSUBISHI ELECTRIC M5M5V408BFP/TP/RT/KV/KR revision-K1.0e, ' 98.09.07 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM MITSUBISHI LSIs 7 Note 3: Hatching indicates the state is "don't care". Note 4: A Write occurs during the overlap of a low S and a low W. Note 5: If W goes low simultaneously with or prior to S,the output remains in the high impedance state. Note 6: Don't apply inverted phase signal externally when DQ pin is in output mode. th (D) tsu (D) DQ1~8 tsu (S) trec (W) tsu (A) tCW A0~18 W S Write cycle (S control mode) DATA IN STABLE (Note3) (Note3) (Note4) (Note5) |
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