K4S640432E

CMOS SDRAM

Rev.0.1 Sept. 2001

The K4S640432E is 67,108,864 bits synchronous high data

rate Dynamic RAM organized as 4 x 4,194,304 words by 4 bits,

fabricated with SAMSUNG

′s high performance CMOS technol-

ogy. Synchronous design allows precise cycle control with the

use of system clock I/O transactions are possible on every clock

cycle. Range of operating frequencies, programmable burst

length and programmable latencies allow the same device to be

useful for a variety of high bandwidth, high performance mem-

ory system applications.

• JEDEC standard 3.3V power supply

• LVTTL compatible with multiplexed address

• Four banks operation

• MRS cycle with address key programs

-. CAS latency (2 & 3)

-. Burst length (1, 2, 4, 8 & Full page)

-. Burst type (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system

clock

• Burst read single-bit write operation

• DQM for masking

• Auto & self refresh

• 64ms refresh period (4K cycle)

GENERAL DESCRIPTION

FEATURES

FUNCTIONAL BLOCK DIAGRAM

4M x 4Bit x 4 Banks Synchronous DRAM

ORDERING INFORMATION

Part No.

Max Freq.

Interface Package

K4S640432E-TC/L75

133MHz(CL=3)

LVTTL

54

TSOP(II)

K4S640432E-TC/L1H

100MHz(CL=2)

K4S640432E-TC/L1L

100MHz(CL=3)

Bank Select

Data Input Register

4M x 4

4M x 4

Column Decoder

Latency & Burst Length

Programming Register

LCKE

LRAS

LCBR

LWE

LDQM

CLK

CKE

CS

RAS

CAS

WE

DQM

LWE

LDQM

DQi

CLK

ADD

LCAS

LWCBR

4M x 4

4M x 4

Timing Register

Samsung Electronics reserves the right to change products or specification without notice.

*