6.42

IDT709079S/L

Preliminary

High-Speed 32K x 8 Synchronous Pipelined Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

8

Timing Waveform of Read Cycle for Flow-Through Output on Right Port

Timing Waveform of Read Cycle for Pipelined Operation

An

An + 1

An + 2

An + 3

R/

W

ADDRESS

CLK

OE

Qn

Qn + 1

Qn + 2

3495 drw 06

(1)

(1)

(1)

(1)

(2)

(4)

(5)

An

An + 1

An + 2

An + 3

R/

W

ADDRESS

CLK

(4)

OE

Qn

Qn + 1

Qn + 2

3495 drw 07

(1)

(1)

(1)

(2)

(5)

(1 Latency)

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.

use only.

6. "x" denotes Left or Right port. The diagram is with respect to that port.