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AS8S512K32 Datasheet(PDF) 4 Page - Austin Semiconductor |
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AS8S512K32 Datasheet(HTML) 4 Page - Austin Semiconductor |
4 / 12 page SRAM AS8S512K32 & AS8S512K32A Austin Semiconductor, Inc. AS8S512K32 & AS8S512K32A Rev. 3.1 12/01 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 AC TEST CONDITIONS NOTE: 1. This parameter is sampled. OH OL I I Current Source Current Source Vz = 1.5V (Bipolar Supply) Device Under Test Ceff = 50pf -+ + NOTES: Vz is programmable from -2V to + 7V. I OL and IOH programmable from 0 to 16 mA. Vz is typically the midpoint of V OH and VOL. I OL and IOH are adjusted to simulate a typical resistive load circuit. Input pulse levels.........................................VSS to 3V Input rise and fall times.........................................5ns Input timing reference levels...............................1.5V Output reference levels........................................1.5V Output load..............................................See Figure 1 Test Specifications SYMBOL PARAMETER MAX UNITS CADD A0 - A18 Capacitance 50 pF COE OE\ Capacitance 50 pF CWE, CCS WE\ and CS\ Capacitance 20 pF CIO I/O 0- I/O 31 Capacitance 20 pF CWE ("A" version) WE\ Capacitance 50 pF CAPACITANCE (V IN = 0V, f = 1MHz, TA = 25 oC)1 Figure 1 |
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