SMS45GCR05 datasheet(10/20 Pages) SUMMIT

Part #	SMS45GCR05

Description	Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory

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Manufacturer	SUMMIT [Summit Microelectronics, Inc.]

Direct Link	http://www.summitmicro.com

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10 / 20 page

10

SMS45

2079 1.2 05/24/04

SUMMIT MICROELECTRONICS, Inc.

Preliminary Information

Table 2. Configuration Register 4

CONFIGURATION REGISTERS

SUPPLY AND MONITOR FUNCTIONS

The V0, V1, V2, and V3 inputs are internally diode-ORed so

that any one of the four can act as the device supply. The

RESET# output will be guaranteed true so long as one of

the four pins is at or above 1V.

Note: for performing a memory operation (Read

or Write) and to have the ability to change

configuration register contents at least one sup-

ply input must be above 2.7V.

Read/Write operations require a 0.1µF capacitor from the

VDD_CAP node to GND.

For optimum performance

connect capacitors from each of the Vx inputs to GND.

Locate the capacitors as physically close to the SMS45 as

possible.

If cascading is enabled, the designer must insure V0 is the

primary supply and is the first to become active.

Associated with each input is a comparator with a program-

mable threshold for detection of under-voltage or over-

voltage conditions on any of the four supply inputs. The

threshold can be programmed in 5mV increments any-

where within the range of 0.6V to 1.875V or 15mV incre-

ments within the range of 1.8V to 5.625V. Configuration

registers 0, 1, 2, and 3 adjust the thresholds for V0, V1, V2,

and V3 respectively.

If the value contained in any register is all zeroes, the

corresponding threshold will be 0.6V. If the contents were

low range 05HEX the threshold would then be 0.625V [0.6V

+ (5

× 0.005V)]. All four registers are configured as 8-Bit

registers.

Table 1. Configuration Registers 0, 1, 2, and 3

RESET FUNCTION AND THRESHOLD RANGE

The reset output has four programmable sources for

activation. Configuration register 4 is used for selecting the

activation source (D7:4), which can be any combination of

V0, V1, V2 and V3. A monitor input can be programmed to

activate on either an under-voltage or over-voltage condi-

tion. The low-order four bits of configuration register 5

program these options. The reset threshold voltage range

for V0 to V3 can be set for 5mV increments below 1.875V

(low Range = "0") or for 15mV increments above 1.8V (high

range = "1") using Bits D3:0.

The RESET# output will become active when triggered by

a selected activation source such as an under-voltage

condition on V1. When this condition ceases, the RESET#

output will remain active for tPRTO (programmable reset

time-out). This reset time-out interval takes priority over

the PUP outputs for use of the timer.

The RESET# output has two hardwired sources for activa-

tion: the MR# input, and the expiration of the Watchdog

timer. RESET# will remain active so long as MR# is low,

and will continue driving the RESET# output for tPRTO

(programmable reset time out) after MR# returns high. The

MR# input cannot be bypassed or disabled.

Refer to Figures 2, 3 and 4 for a detailed illustration of the

relationships among the affected signals.

The status of the four supplies is available at any time over

the I2C bus in the high order configuration bits of register 5

(Table 3). A "1" in a bit location indicates a fault on that

supply.

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