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SMM105NER00 Datasheet(PDF) 9 Page - Summit Microelectronics, Inc. |
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SMM105NER00 Datasheet(HTML) 9 Page - Summit Microelectronics, Inc. |
9 / 21 page SMM105 Preliminary Information Summit Microelectronics, Inc 2068 1.8 09/20/05 9 STATUS REGISTER A status register exists for I 2C polling of the status of the COMP1 and COMP2 inputs. Two bits in this status register reflect the current state of the inputs (1 = fault, 0 = no fault). Two additional bits show the state of the inputs latched by one of two events programmed in the configuration. The first event option is the FAULT# output going active. The second event option is the READY pin going low. The READY pin is an I/O. As an output, the READY output pin goes active when the DC controlled voltages are at their set point. As an input programmed to active high, it can be pulled low externally and latch the state of the COMP inputs. This second event option allows the state of the COMP inputs on multiple devices to be latched at the same time while a host monitors their FAULT# outputs. MARGINING The SMM105 has two additional Active DC Output Control voltage settings: margin high and margin low. The margin high and margin low settings can be as much as ±10% of the nominal setting depending on the manufacturer. The SMM105 range can be as large as VREF_CNTL to VDD. These settings are stored in the configuration registers and are loaded into the Active DC Output Control voltage setting by margin commands issued via the I 2C bus. The device must be enabled for Active DC Output Control in order to enable margining. The margin command registers contain two bits that decode the commands to margin high, margin low, or control to the nominal setting. Once the SMM105 receives the command to margin the supply voltage, it begins adjusting the supply voltage to move toward the desired setting. When this voltage setting is reached, a bit is set in the margin status registers and the READY signal becomes active. (Figure 5) Note: Configuration writes or reads of registers 00HEX to 03HEX should not be performed while the SMM105 is margining. WRITE PROTECTION Write protection for the SMM105 is located in a volatile register where the power-on state is defaulted to write protect. There are separate write protect modes for the configuration registers and memory. In order to remove write protection, the code 55HEX is written to the write protection register. Other codes will enable write protection. For example, writing 59HEX will allow writes to the configuration register but not to the memory, while writing 35HEX will allow writes to the memory but not to the configuration registers. The SMM105 also features a Write Protect pin (WP# input) which, when asserted, prevents writing to the configuration registers and EE memory. In addition to these two forms of write protection there is a configuration register lock bit which, once programmed, does not allow the configuration registers to be changed. F Figure 5 – SMM105 margin example. The nominal setting is 1.8V. The device margins the DC-DC converter from nominal to high, 2.0V then to nominal, then to low, 1.6V. Next it margins to nominal then high and then from high to low and to high again. The READY signals goes low when margining and high when complete. APPLICATIONS INFORMATION (CONTINUED) |
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