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SP674AS Datasheet(PDF) 10 Page - Sipex Corporation |
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SP674AS Datasheet(HTML) 10 Page - Sipex Corporation |
10 / 14 page 12 Conversion Length A conversion start transition latches the state of A 0 as shown in Figure 8 and Table 1. The latched state determines if the conversion stops with 8– bits (A 0 high) or continues for 12–bits (A0 low). If all 12–bits are read following an 8–bit conver- sion, the three LSB’s will be a logic “0” and DB 3 will be a logic “1”. A 0 is latched because it is also involved in enabling the output buffers as ex- plained elsewhere. No other control inputs are latched. Stand–Alone Operation The simplest interface is a control line connected to R/C. The other controls must be tied to known states as follows: CE and 12/8 are wired high, A 0 and CS are wired low. The output data arrives in words of 12–bits each. The limits on R/C duty cycle are shown in Figures 9 and 10. The duty cycle may be within and including the extremes shown in the specifications. In general, data may be read when R/C is high unless STS is also high, indicating a conversion is in progress. Reading Output Data The output data buffers remain in a high imped- ance state until the following four conditions are met: R/C is high, STS is low, CE is high and CS is low. The data lines become active in response to these four conditions, and output data accord- ing to the conditions of the control lines 12/8 and A 0. The timing diagram for this process is shown in Figure 11. When 12/8 is high, all 12 data outputs become active simultaneously and the A 0 input is ignored. The 12/8 input is usually tied high or low; it is TTL/CMOS compatible. When 12/8 is low, the output is separated into two 8–bit bytes as shown below: BYTE 1 BYTE2 xxxx xxxx xxxx 0000 MSB LSB This configuration makes it easy to connect to an 8–bit address bus as shown in Figure 7. The A 0 control can be connected to the least significant bit of the data bus in order to store the output data into two consecutive memory locations. When A 0 is pulled low, the 8 MSB’s are enabled only. When A 0 is high, the 8 MSB’s are disabled, bits 4 through 7 are forced to a zero and the four LSB’s are enabled. The two byte format is “left justified data” as shown above and can be con- sidered to have a decimal point or binary to the left of byte 1. A 0 may be toggled without damage to the con- verter at any time. Break–before–make action is guaranteed between the two data bytes. This assures that the outputs which are strapped to- gether in Figure 11 will never be enabled at the same time. In Figure 11, it can be seen that a read operation usually begins after the conversion is complete and STS is low. If earlier access is needed, the read can begin no later than the addition of times t DD and tHS before STS goes low. Figure 7. Interfacing SPx74A to 8–Bit Interface Bus 28 27 26 25 24 23 22 21 20 19 18 17 16 15 STS DB11 (MSB) DB0 (LSB) DIG COM SPx74A 2 4 A0 ADDRESS BUS A0 12/8 DATA BUS |
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