C9870G
High Performance Pentium® 4 Clock Synthesizer
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07108 Rev. *A
12/26/2002
Page 4 of 25
Approved Product
Serial Control Registers (Cont.)
Byte 0: CPU Clock Register
Bit
@Pup
Pin#
Description
7
0
-
Spread Spectrum Enable
0 = Spread Off, 1 = Spread On
This is a Read and Write control bit.
6
0
-
Reserved
5
0
35
3V66_1/VCH frequency Select
0 = 66M selected, 1 = 48M selected
This is a Read and Write control bit.
4
Pin 53
44,45,48,49,
51,52
CPU_STP#. Reflects the current value of the external CPU_STP# (pin 53) This bit is Read Only.
3
Pin 34
10,11,12,13,
16,17,18
Reflects the current value of the internal PCI_STP# function when read. Internally PCI_STP# is a
logical AND function of the internal SMBus register bit and the external PCI_STP# pin.
2
Pin 40
-
Frequency Select Bit 2. Reflects the value of SEL2 (pin 40). This bit is Read Only.
1
Pin 55
-
Frequency Select Bit 1. Reflects the value of SEL1 (pin 55). This bit is Read Only.
0
Pin 54
-
Frequency Select Bit 0. Reflects the value of SEL0 (pin 54). This bit is Read Only.
Byte 1: CPU Clock Register
Bit
@Pup
Pin#
Description
7
Pin 43
-
MULT0 (Pin 43) Value. This bit is Read Only.
6
0
-
Reserved
5
0
44,45
Controls CPU2 functionality when CPU_STP# is asserted LOW
1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW
This is a Read and Write control bit.
4
0
48,49
Controls CPU1 functionality when CPU_STP# is asserted LOW
1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW
This is a Read and Write control bit.
3
0
51,52
Controls CPU0 functionality when CPU_STP# is asserted LOW
1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW
This is a Read and Write control bit.
2
1
44,45
CPU2 Output Control, 1 = enabled, 0 = disable HIGH and CPU/2 disables LOW
This is a Read and Write control bit.
1
1
48,49
CPU1 Output Control, 1 = enabled, 0 = disable HIGH and CPU/1 disables LOW
This is a Read and Write control bit.
0
1
51,52
CPU0 Output Control, 1 = enabled, 0 = disable HIGH and CPU/0 disables LOW
This is a Read and Write control bit.
Byte 2: PCI Clock Control Register
(all bits are read and write functional)
Bit
@Pup
Pin#
Description
7
0
-
Reserved
6
1
18
PCI6 Output Control
1 = enabled, 0 = forced LOW
5
1
17
PCI5 Output Control
1 = enabled, 0 = forced LOW
4
1
16
PCI4 Output Control
1 = enabled, 0 = forced LOW
3
1
13
PCI3 Output Control
1 = enabled, 0 = forced LOW
2
1
12
PCI2 Output Control
1 = enabled, 0 = forced LOW
1
1
11
PCI1 Output Control
1 = enabled, 0 = forced LOW
0
1
10
PCI0 Output Control
1 = enabled, 0 = forced LOW
Byte 3: PCI_F Clock and 48M Control Register
(all bits are read and write functional)
Bit
@Pup
Pin#
Description
7
1
38
48MDOT Output Control
1 = enabled, 0 = forced LOW
6
1
39
48MUSB Output Control
1 = enabled, 0 = forced LOW
5
0
7
PCI_STP#, control of PCI_F2.
0 = Free Running, 1 = Stopped when
PCI_STP# is LOW
4
0
6
PCI_STP#, control of PCI_F1.
0 = Free Running, 1 = Stopped when
PCI_STP# is LOW
3
0
5
PCI_STP#, control of PCI_F0.
0 = Free Running, 1 = Stopped when
PCI_STP# is LOW
2
1
7
PCI_F2 Output Control
1=running, 0=forced LOW
1
1
6
PCI_F1 Output Control
1= running, 0=forced LOW
0
1
5
PCI_F0 Output Control
1= running, 0=forced LOW