APPLICATION NOTES

IN

AL,BL,CL - Are the lowside logic level digital inputs.

These

three inputs control the three lowside bridge transistors. If the

highside inputs are low, then the lowside inputs will control

both the lowside and the highside of the bridge, with deadtime

set by the SWR resistor. EN will override these inputs, forcing

all outputs low. These inputs can be driven by logic up to 15V

(less than VBIAS). An internal pullup to VBIAS will hold each

input high if the pins are not driven.

MSK 4401 PIN DESCRIPTIONS

AH,BH,CH - Are the highside logic level digital inputs. These

three inputs control the three highside bridge transistors. Un-

less the deadtime is disabled by connecting SWR to ground, the

lowside input of each phase will override the corresponding

highside input. If SWR is the lowside input of each phase will

override the corresponding highside input.

In this condition,

tied to ground, deadtime is disabled and the outputs follow the

inputs. In this condition, shoot-through must be avoided exter-

nally. EN will override all inputs, forcing outputs low.

VBIAS - Is the positive supply for the gate drive. This pin should

be decoupled to ground with at least a 22µF capacitor in parallel

with a 0.1µF ceramic capacitor.

GROUND - Is the return for the VBIAS supply. This pin should

be connected to the return of the lowside MOSFETs or the bot-

tom of the sense resistor at the bottom of the bridge. The gate

drive current must return through this pin, so trace lengths should

be kept to a minimum. All grounds should be returned to the

bottom of the bridge or sense resistor in a star fashion. This

will eliminate ground loops.

SWR - Is the pin for controlling the deadtime between the top

and bottom transistors of the bridge. By connecting a pullup

resistor between this pin and VBIAS, various deadtimes can be

obtained. There is and internal 100K

Ω pullup resistor connected

internally. By adding additional resistors in externally, reduced

deadtimes can be achieved. By connecting this pin directly to

ground, all deadtime is eliminated. However, care must be taken

to assure that deadtime is being generated by the logic circuitry

driving the inputs. Shoot-through can occur (both the top and

bottom transistors on at the same time for a given phase, caus-

ing a short on the V+ supply to ground) destroying the bridge.

V+ - Is the power connection for the top of the output bridge.

These pins must be bypassed by a capacitor to ground of a

least 10µF per amp preferrably 100µF per amp of output current

minimum, high quality high frequency bypass capacitance to

help suppress switching noise. Connect both pins for proper

current sharing.

A

bridge. Connect both pins for proper current sharing.

The size and placement of the capacitors for the main voltage

bus for the motor will have an effect on the noise filtered through-

out the rest of the system. Series RLC tuned circuit is being

created by the inductance of the wire (about 30nH per inch),

the filter capacitance, and all of the resistances (wire resistance

and the capacitor ESR) of the overall power circuit. Voltage

spikes from the back EMF if the motor ride on top of the bus

voltage. All of this must be taken into account when laying out

the system. A first capacitor of high quality and low ESR should

be placed as close to the hybrid circuit as possible. Along with

that, a capacitor of 5x to 10x the first value should be added

(and that second capacitor should have some ESR) and/or a

resistor should be added to help with the damping of the volt-

age spikes. Be careful of the ripple current in all the capacitors.

Excessive ripple current, beyond what the capacitor is rated

for, will destroy the capacitor.

BUS VOLTAGE FILTER CAPACITORS

It is recommended that at least 22µF of capacitance for by-

passing the VBIAS voltage that supplies the drive circuitry for

the MSK 4401, along with 0.1µF for helping the high frequency

current pulses needed by the gate driver. If an extremely long

risetime is exhibited by the turn on of the FETs, the extra high

frequency capacitance will help.

BIAS SUPPLY BYPASS CAPACITORS

Good high frequency PC layout techniques are a must. Traces

wide enough for the current delivered, and placement of the big

capacitors close to the MSK 4401 are very important.

The

path for the RSENSE connection through any sense resistor

back to the GND pins must be as short as possible. This path is

the gate drive current path for all the FETs on the lower half of

each phase. A short, low inductance path will aid in the switch-

ing time of those FETs.

GENERAL LAYOUT

When starting up the circuit utilizing the MSK 4401 for the first

time, it is very important to keep certain things in mind. Be-

cause of the small size of the bridge, there is no internal short

circuit protection and a short circuit will destroy the bridge.

Any required short circuit protection must be built outside the

bridge. Current and voltage limit the power supply feeding the

V+ pins to the bridge, and monitor the current for any signs of

short circuiting, or shoot-through currents. If there are large

current spikes at the beginning of each switching cycle, there

may be shoot through.

Try raising the resistor value of the

SWR. This will lengthen the deadtime and stop shoot-through.

LOW POWER STARTUP

Rev. E 11/04

3

EN - Is the enabling input for the bridge. This digital input,

when pulled low, will enable the bridge, following the inputs

from AL, BL, CL and AH, BH, CH inputs. When pulled high, it

will override all other inputs and disable the bridge. It is inter-

nally pulled high to VBIAS, and can be driven by logic levels up

to VBIAS.

RSENSE - Are the connections to the bottom of the bridge. All

power flowing through the bridge will flow through this point,

and can be sensed by connecting a sense resistor from here to

ground. The sense resistor will develop a voltage proportional

to the current flowing. Size the value and power rating of the

sense resistor according to the voltage necessary. 3 volts is the

maximum voltage between this point and ground, or damage to

the hybrid will result. Connect both pins for proper current shar-

ing.